1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Balaji Krishnamoorthy <balajitk@ti.com> 6*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef _SDP4430_MUX_DATA_H 11*4882a593Smuzhiyun #define _SDP4430_MUX_DATA_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/arch/mux_omap4.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun const struct pad_conf_entry core_padconf_array_essential[] = { 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ 18*4882a593Smuzhiyun {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ 19*4882a593Smuzhiyun {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ 20*4882a593Smuzhiyun {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ 21*4882a593Smuzhiyun {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ 22*4882a593Smuzhiyun {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ 23*4882a593Smuzhiyun {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ 24*4882a593Smuzhiyun {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ 25*4882a593Smuzhiyun {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ 26*4882a593Smuzhiyun {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ 27*4882a593Smuzhiyun {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ 28*4882a593Smuzhiyun {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ 29*4882a593Smuzhiyun {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ 30*4882a593Smuzhiyun {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ 31*4882a593Smuzhiyun {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ 32*4882a593Smuzhiyun {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ 33*4882a593Smuzhiyun {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ 34*4882a593Smuzhiyun {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ 35*4882a593Smuzhiyun {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ 36*4882a593Smuzhiyun {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ 37*4882a593Smuzhiyun {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ 38*4882a593Smuzhiyun {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ 39*4882a593Smuzhiyun {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ 40*4882a593Smuzhiyun {UART3_TX_IRTX, (M0)}, /* uart3_tx */ 41*4882a593Smuzhiyun {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ 42*4882a593Smuzhiyun {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ 43*4882a593Smuzhiyun {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ 44*4882a593Smuzhiyun {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ 45*4882a593Smuzhiyun {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ 46*4882a593Smuzhiyun {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ 47*4882a593Smuzhiyun {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ 48*4882a593Smuzhiyun {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ 49*4882a593Smuzhiyun {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ 50*4882a593Smuzhiyun {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ 51*4882a593Smuzhiyun {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun const struct pad_conf_entry wkup_padconf_array_essential[] = { 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ 57*4882a593Smuzhiyun {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ 58*4882a593Smuzhiyun {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _SDP4430_MUX_DATA_H */ 69