1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Keystone2: DDR3 initialization 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2012-2014 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include "ddr3_cfg.h" 12*4882a593Smuzhiyun #include <asm/arch/ddr3.h> 13*4882a593Smuzhiyun #include <asm/arch/hardware.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); 16*4882a593Smuzhiyun struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); 17*4882a593Smuzhiyun ddr3_init(void)18*4882a593Smuzhiyunu32 ddr3_init(void) 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun u32 ddr3_size; 21*4882a593Smuzhiyun struct ddr3_spd_cb spd_cb; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun if (ddr3_get_dimm_params_from_spd(&spd_cb)) { 24*4882a593Smuzhiyun printf("Sorry, I don't know how to configure DDR3A.\n" 25*4882a593Smuzhiyun "Bye :(\n"); 26*4882a593Smuzhiyun for (;;) 27*4882a593Smuzhiyun ; 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun if ((cpu_revision() > 1) || 33*4882a593Smuzhiyun (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) { 34*4882a593Smuzhiyun printf("DDR3 speed %d\n", spd_cb.ddrspdclock); 35*4882a593Smuzhiyun if (spd_cb.ddrspdclock == 1600) 36*4882a593Smuzhiyun init_pll(&ddr3a_400); 37*4882a593Smuzhiyun else 38*4882a593Smuzhiyun init_pll(&ddr3a_333); 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun if (cpu_revision() > 0) { 42*4882a593Smuzhiyun if (cpu_revision() > 1) { 43*4882a593Smuzhiyun /* PG 2.0 */ 44*4882a593Smuzhiyun /* Reset DDR3A PHY after PLL enabled */ 45*4882a593Smuzhiyun ddr3_reset_ddrphy(); 46*4882a593Smuzhiyun spd_cb.phy_cfg.zq0cr1 |= 0x10000; 47*4882a593Smuzhiyun spd_cb.phy_cfg.zq1cr1 |= 0x10000; 48*4882a593Smuzhiyun spd_cb.phy_cfg.zq2cr1 |= 0x10000; 49*4882a593Smuzhiyun } 50*4882a593Smuzhiyun ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ddr3_size = spd_cb.ddr_size_gbyte; 55*4882a593Smuzhiyun } else { 56*4882a593Smuzhiyun ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); 57*4882a593Smuzhiyun spd_cb.emif_cfg.sdcfg |= 0x1000; 58*4882a593Smuzhiyun ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); 59*4882a593Smuzhiyun ddr3_size = spd_cb.ddr_size_gbyte / 2; 60*4882a593Smuzhiyun } 61*4882a593Smuzhiyun printf("DRAM: %d GiB (includes reported below)\n", ddr3_size); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Apply the workaround for PG 1.0 and 1.1 Silicons */ 64*4882a593Smuzhiyun if (cpu_revision() <= 1) 65*4882a593Smuzhiyun ddr3_err_reset_workaround(); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun return ddr3_size; 68*4882a593Smuzhiyun } 69