1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * K2L EVM : Board initialization
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2014
5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/arch/ddr3.h>
12*4882a593Smuzhiyun #include <asm/arch/hardware.h>
13*4882a593Smuzhiyun #include <asm/ti-common/keystone_net.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
get_external_clk(u32 clk)17*4882a593Smuzhiyun unsigned int get_external_clk(u32 clk)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun unsigned int clk_freq;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun switch (clk) {
22*4882a593Smuzhiyun case sys_clk:
23*4882a593Smuzhiyun clk_freq = 122880000;
24*4882a593Smuzhiyun break;
25*4882a593Smuzhiyun case alt_core_clk:
26*4882a593Smuzhiyun clk_freq = 100000000;
27*4882a593Smuzhiyun break;
28*4882a593Smuzhiyun case pa_clk:
29*4882a593Smuzhiyun clk_freq = 122880000;
30*4882a593Smuzhiyun break;
31*4882a593Smuzhiyun case tetris_clk:
32*4882a593Smuzhiyun clk_freq = 122880000;
33*4882a593Smuzhiyun break;
34*4882a593Smuzhiyun case ddr3a_clk:
35*4882a593Smuzhiyun clk_freq = 100000000;
36*4882a593Smuzhiyun break;
37*4882a593Smuzhiyun default:
38*4882a593Smuzhiyun clk_freq = 0;
39*4882a593Smuzhiyun break;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return clk_freq;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static struct pll_init_data core_pll_config[NUM_SPDS] = {
46*4882a593Smuzhiyun [SPD800] = CORE_PLL_799,
47*4882a593Smuzhiyun [SPD1000] = CORE_PLL_1000,
48*4882a593Smuzhiyun [SPD1200] = CORE_PLL_1198,
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun s16 divn_val[16] = {
52*4882a593Smuzhiyun 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static struct pll_init_data tetris_pll_config[] = {
56*4882a593Smuzhiyun [SPD800] = TETRIS_PLL_799,
57*4882a593Smuzhiyun [SPD1000] = TETRIS_PLL_1000,
58*4882a593Smuzhiyun [SPD1200] = TETRIS_PLL_1198,
59*4882a593Smuzhiyun [SPD1350] = TETRIS_PLL_1352,
60*4882a593Smuzhiyun [SPD1400] = TETRIS_PLL_1401,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static struct pll_init_data pa_pll_config =
64*4882a593Smuzhiyun PASS_PLL_983;
65*4882a593Smuzhiyun
get_pll_init_data(int pll)66*4882a593Smuzhiyun struct pll_init_data *get_pll_init_data(int pll)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun int speed;
69*4882a593Smuzhiyun struct pll_init_data *data;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun switch (pll) {
72*4882a593Smuzhiyun case MAIN_PLL:
73*4882a593Smuzhiyun speed = get_max_dev_speed(speeds);
74*4882a593Smuzhiyun data = &core_pll_config[speed];
75*4882a593Smuzhiyun break;
76*4882a593Smuzhiyun case TETRIS_PLL:
77*4882a593Smuzhiyun speed = get_max_arm_speed(speeds);
78*4882a593Smuzhiyun data = &tetris_pll_config[speed];
79*4882a593Smuzhiyun break;
80*4882a593Smuzhiyun case PASS_PLL:
81*4882a593Smuzhiyun data = &pa_pll_config;
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun default:
84*4882a593Smuzhiyun data = NULL;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return data;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
91*4882a593Smuzhiyun struct eth_priv_t eth_priv_cfg[] = {
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun .int_name = "K2L_EMAC",
94*4882a593Smuzhiyun .rx_flow = 0,
95*4882a593Smuzhiyun .phy_addr = 0,
96*4882a593Smuzhiyun .slave_port = 1,
97*4882a593Smuzhiyun .sgmii_link_type = SGMII_LINK_MAC_PHY,
98*4882a593Smuzhiyun .phy_if = PHY_INTERFACE_MODE_SGMII,
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun .int_name = "K2L_EMAC1",
102*4882a593Smuzhiyun .rx_flow = 8,
103*4882a593Smuzhiyun .phy_addr = 1,
104*4882a593Smuzhiyun .slave_port = 2,
105*4882a593Smuzhiyun .sgmii_link_type = SGMII_LINK_MAC_PHY,
106*4882a593Smuzhiyun .phy_if = PHY_INTERFACE_MODE_SGMII,
107*4882a593Smuzhiyun },
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun .int_name = "K2L_EMAC2",
110*4882a593Smuzhiyun .rx_flow = 16,
111*4882a593Smuzhiyun .phy_addr = 2,
112*4882a593Smuzhiyun .slave_port = 3,
113*4882a593Smuzhiyun .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
114*4882a593Smuzhiyun .phy_if = PHY_INTERFACE_MODE_SGMII,
115*4882a593Smuzhiyun },
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun .int_name = "K2L_EMAC3",
118*4882a593Smuzhiyun .rx_flow = 32,
119*4882a593Smuzhiyun .phy_addr = 3,
120*4882a593Smuzhiyun .slave_port = 4,
121*4882a593Smuzhiyun .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
122*4882a593Smuzhiyun .phy_if = PHY_INTERFACE_MODE_SGMII,
123*4882a593Smuzhiyun },
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
get_num_eth_ports(void)126*4882a593Smuzhiyun int get_num_eth_ports(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun #endif
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)133*4882a593Smuzhiyun int board_early_init_f(void)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun init_plls();
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun #endif
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #if defined(CONFIG_MULTI_DTB_FIT)
board_fit_config_name_match(const char * name)142*4882a593Smuzhiyun int board_fit_config_name_match(const char *name)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun if (!strcmp(name, "keystone-k2l-evm"))
145*4882a593Smuzhiyun return 0;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return -1;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun #endif
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
spl_init_keystone_plls(void)152*4882a593Smuzhiyun void spl_init_keystone_plls(void)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun init_plls();
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun #endif
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