1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Base addresses for the SPI direct access mode */ 8*4882a593Smuzhiyun #define SPI_BUS0_DEV1_BASE 0xe0000000 9*4882a593Smuzhiyun #define SPI_BUS0_DEV1_SIZE (1 << 20) 10*4882a593Smuzhiyun #define SPI_BUS1_DEV2_BASE (SPI_BUS0_DEV1_BASE + SPI_BUS0_DEV1_SIZE) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun void board_fpga_add(void); 13