xref: /OK3568_Linux_fs/u-boot/board/technexion/tao3530/tao3530.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Maintainer :
3*4882a593Smuzhiyun  *      Tapani Utriainen <linuxfae@technexion.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <netdev.h>
9*4882a593Smuzhiyun #include <twl4030.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/mmc_host_def.h>
12*4882a593Smuzhiyun #include <asm/arch/mem.h>
13*4882a593Smuzhiyun #include <asm/arch/mux.h>
14*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
15*4882a593Smuzhiyun #include <asm/arch/gpio.h>
16*4882a593Smuzhiyun #include <asm/gpio.h>
17*4882a593Smuzhiyun #include <asm/mach-types.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <usb.h>
20*4882a593Smuzhiyun #include <asm/ehci-omap.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include "tao3530.h"
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
25*4882a593Smuzhiyun 
tao3530_revision(void)26*4882a593Smuzhiyun int tao3530_revision(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun 	int ret = 0;
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	/* char *label argument is unused in gpio_request() */
31*4882a593Smuzhiyun 	ret = gpio_request(65, "");
32*4882a593Smuzhiyun 	if (ret) {
33*4882a593Smuzhiyun 		puts("Error: GPIO 65 not available\n");
34*4882a593Smuzhiyun 		goto out;
35*4882a593Smuzhiyun 	}
36*4882a593Smuzhiyun 	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M4));
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	ret = gpio_request(1, "");
39*4882a593Smuzhiyun 	if (ret) {
40*4882a593Smuzhiyun 		puts("Error: GPIO 1 not available\n");
41*4882a593Smuzhiyun 		goto out2;
42*4882a593Smuzhiyun 	}
43*4882a593Smuzhiyun 	MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTU | EN | M4));
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	ret = gpio_direction_input(65);
46*4882a593Smuzhiyun 	if (ret) {
47*4882a593Smuzhiyun 		puts("Error: GPIO 65 not available for input\n");
48*4882a593Smuzhiyun 		goto out3;
49*4882a593Smuzhiyun 	}
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	ret =  gpio_direction_input(1);
52*4882a593Smuzhiyun 	if (ret) {
53*4882a593Smuzhiyun 		puts("Error: GPIO 1 not available for input\n");
54*4882a593Smuzhiyun 		goto out3;
55*4882a593Smuzhiyun 	}
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	ret = gpio_get_value(65) << 1 | gpio_get_value(1);
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun out3:
60*4882a593Smuzhiyun 	MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTU | EN | M0));
61*4882a593Smuzhiyun 	gpio_free(1);
62*4882a593Smuzhiyun out2:
63*4882a593Smuzhiyun 	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0));
64*4882a593Smuzhiyun 	gpio_free(65);
65*4882a593Smuzhiyun out:
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	return ret;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun  * Routine: get_board_mem_timings
73*4882a593Smuzhiyun  * Description: If we use SPL then there is no x-loader nor config header
74*4882a593Smuzhiyun  * so we have to setup the DDR timings ourself on both banks.
75*4882a593Smuzhiyun  */
get_board_mem_timings(struct board_sdrc_timings * timings)76*4882a593Smuzhiyun void get_board_mem_timings(struct board_sdrc_timings *timings)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun #if defined(CONFIG_SYS_BOARD_OMAP3_HA)
79*4882a593Smuzhiyun 	/*
80*4882a593Smuzhiyun 	 * Switch baseboard LED to red upon power-on
81*4882a593Smuzhiyun 	 */
82*4882a593Smuzhiyun 	MUX_OMAP3_HA();
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	/* Request a gpio before using it */
85*4882a593Smuzhiyun 	gpio_request(111, "");
86*4882a593Smuzhiyun 	/* Sets the gpio as output and its value to 1, switch LED to red */
87*4882a593Smuzhiyun 	gpio_direction_output(111, 1);
88*4882a593Smuzhiyun #endif
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	if (tao3530_revision() < 3) {
91*4882a593Smuzhiyun 		/* 256MB / Bank */
92*4882a593Smuzhiyun 		timings->mcfg = MCFG(256 << 20, 14);	/* RAS-width 14 */
93*4882a593Smuzhiyun 		timings->ctrla = HYNIX_V_ACTIMA_165;
94*4882a593Smuzhiyun 		timings->ctrlb = HYNIX_V_ACTIMB_165;
95*4882a593Smuzhiyun 	} else {
96*4882a593Smuzhiyun 		/* 128MB / Bank */
97*4882a593Smuzhiyun 		timings->mcfg = MCFG(128 << 20, 13);	/* RAS-width 13 */
98*4882a593Smuzhiyun 		timings->ctrla = MICRON_V_ACTIMA_165;
99*4882a593Smuzhiyun 		timings->ctrlb = MICRON_V_ACTIMB_165;
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	timings->mr = MICRON_V_MR_165;
103*4882a593Smuzhiyun 	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun #endif
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun  * Routine: board_init
109*4882a593Smuzhiyun  * Description: Early hardware init.
110*4882a593Smuzhiyun  */
board_init(void)111*4882a593Smuzhiyun int board_init(void)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
114*4882a593Smuzhiyun 	/* board id for Linux */
115*4882a593Smuzhiyun 	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
116*4882a593Smuzhiyun 	/* boot param addr */
117*4882a593Smuzhiyun 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	return 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /*
123*4882a593Smuzhiyun  * Routine: misc_init_r
124*4882a593Smuzhiyun  * Description: Configure board specific parts
125*4882a593Smuzhiyun  */
misc_init_r(void)126*4882a593Smuzhiyun int misc_init_r(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
129*4882a593Smuzhiyun 	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	twl4030_power_init();
132*4882a593Smuzhiyun 	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	/* Configure GPIOs to output */
135*4882a593Smuzhiyun 	/* GPIO23 */
136*4882a593Smuzhiyun 	writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
137*4882a593Smuzhiyun 	writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
138*4882a593Smuzhiyun 		 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	/* Set GPIOs */
141*4882a593Smuzhiyun 	writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
142*4882a593Smuzhiyun 	       &gpio6_base->setdataout);
143*4882a593Smuzhiyun 	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
144*4882a593Smuzhiyun 	       GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	switch (tao3530_revision()) {
147*4882a593Smuzhiyun 	case 0:
148*4882a593Smuzhiyun 		puts("TAO-3530 REV Reserve 1\n");
149*4882a593Smuzhiyun 		break;
150*4882a593Smuzhiyun 	case 1:
151*4882a593Smuzhiyun 		puts("TAO-3530 REV Reserve 2\n");
152*4882a593Smuzhiyun 		break;
153*4882a593Smuzhiyun 	case 2:
154*4882a593Smuzhiyun 		puts("TAO-3530 REV Cx\n");
155*4882a593Smuzhiyun 		break;
156*4882a593Smuzhiyun 	case 3:
157*4882a593Smuzhiyun 		puts("TAO-3530 REV Ax/Bx\n");
158*4882a593Smuzhiyun 		break;
159*4882a593Smuzhiyun 	default:
160*4882a593Smuzhiyun 		puts("Unknown board revision\n");
161*4882a593Smuzhiyun 	}
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	omap_die_id_display();
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	return 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun /*
169*4882a593Smuzhiyun  * Routine: set_muxconf_regs
170*4882a593Smuzhiyun  * Description: Setting up the configuration Mux registers specific to the
171*4882a593Smuzhiyun  *		hardware. Many pins need to be moved from protect to primary
172*4882a593Smuzhiyun  *		mode.
173*4882a593Smuzhiyun  */
set_muxconf_regs(void)174*4882a593Smuzhiyun void set_muxconf_regs(void)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	MUX_TAO3530();
177*4882a593Smuzhiyun #if defined(CONFIG_SYS_BOARD_OMAP3_HA)
178*4882a593Smuzhiyun 	MUX_OMAP3_HA();
179*4882a593Smuzhiyun #endif
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)183*4882a593Smuzhiyun int board_mmc_init(bd_t *bis)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	omap_mmc_init(0, 0, 0, -1, -1);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	return 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun #endif
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun #if defined(CONFIG_MMC)
board_mmc_power_init(void)192*4882a593Smuzhiyun void board_mmc_power_init(void)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	twl4030_power_mmc_init(0);
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun #endif
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
199*4882a593Smuzhiyun /* Call usb_stop() before starting the kernel */
show_boot_progress(int val)200*4882a593Smuzhiyun void show_boot_progress(int val)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun 	if (val == BOOTSTAGE_ID_RUN_OS)
203*4882a593Smuzhiyun 		usb_stop();
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun static struct omap_usbhs_board_data usbhs_bdata = {
207*4882a593Smuzhiyun 	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
208*4882a593Smuzhiyun 	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
209*4882a593Smuzhiyun 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)212*4882a593Smuzhiyun int ehci_hcd_init(int index, enum usb_init_type init,
213*4882a593Smuzhiyun 		  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
ehci_hcd_stop(int index)218*4882a593Smuzhiyun int ehci_hcd_stop(int index)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	return omap_ehci_hcd_stop();
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun #endif /* CONFIG_USB_EHCI_HCD */
223