xref: /OK3568_Linux_fs/u-boot/board/syteco/zmx25/zmx25.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (c) 2011 Graf-Syteco, Matthias Weisser
3*4882a593Smuzhiyun  * <weisserm@arcor.de>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Based on tx25.c:
6*4882a593Smuzhiyun  * (C) Copyright 2009 DENX Software Engineering
7*4882a593Smuzhiyun  * Author: John Rigby <jrigby@gmail.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Based on imx27lite.c:
10*4882a593Smuzhiyun  *   Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
11*4882a593Smuzhiyun  *   Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
12*4882a593Smuzhiyun  * And:
13*4882a593Smuzhiyun  *   RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <asm/gpio.h>
19*4882a593Smuzhiyun #include <asm/io.h>
20*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
21*4882a593Smuzhiyun #include <asm/arch/iomux-mx25.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
24*4882a593Smuzhiyun 
board_init()25*4882a593Smuzhiyun int board_init()
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun 	static const iomux_v3_cfg_t sdhc1_pads[] = {
28*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
29*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
30*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
31*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
32*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
33*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
34*4882a593Smuzhiyun 	};
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	static const iomux_v3_cfg_t dig_out_pads[] = {
37*4882a593Smuzhiyun 		MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
38*4882a593Smuzhiyun 		MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
39*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
40*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
41*4882a593Smuzhiyun 	};
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	static const iomux_v3_cfg_t led_pads[] = {
44*4882a593Smuzhiyun 		MX25_PAD_CSI_D9__GPIO_4_21,
45*4882a593Smuzhiyun 		MX25_PAD_CSI_D4__GPIO_1_29,
46*4882a593Smuzhiyun 	};
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	static const iomux_v3_cfg_t can_pads[] = {
49*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
50*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
51*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
52*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
53*4882a593Smuzhiyun 	};
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	static const iomux_v3_cfg_t i2c3_pads[] = {
56*4882a593Smuzhiyun 		MX25_PAD_CSPI1_SS1__I2C3_DAT,
57*4882a593Smuzhiyun 		MX25_PAD_GPIO_E__I2C3_CLK,
58*4882a593Smuzhiyun 	};
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	icache_enable();
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	/* Setup of core voltage selection pin to run at 1.4V */
63*4882a593Smuzhiyun 	imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
64*4882a593Smuzhiyun 	gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	/* Setup of SD card pins*/
67*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	/* Setup of digital output for USB power and OC */
70*4882a593Smuzhiyun 	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
71*4882a593Smuzhiyun 	gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
74*4882a593Smuzhiyun 	gpio_direction_input(IMX_GPIO_NR(1, 18));
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	/* Setup of digital output control pins */
77*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(dig_out_pads,
78*4882a593Smuzhiyun 						ARRAY_SIZE(dig_out_pads));
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* Switch both output drivers off */
81*4882a593Smuzhiyun 	gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
82*4882a593Smuzhiyun 	gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	/* Setup of key input pin */
85*4882a593Smuzhiyun 	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
86*4882a593Smuzhiyun 	gpio_direction_input(IMX_GPIO_NR(2, 29));
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	/* Setup of status LED outputs */
89*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	/* Switch both LEDs off */
92*4882a593Smuzhiyun 	gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
93*4882a593Smuzhiyun 	gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/* Setup of CAN1 and CAN2 signals */
96*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	/* Setup of I2C3 signals */
99*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
board_late_init(void)106*4882a593Smuzhiyun int board_late_init(void)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	const char *e;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #ifdef CONFIG_FEC_MXC
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun  * FIXME: need to revisit this
113*4882a593Smuzhiyun  * The original code enabled PUE and 100-k pull-down without PKE, so the right
114*4882a593Smuzhiyun  * value here is likely:
115*4882a593Smuzhiyun  *	0 for no pull
116*4882a593Smuzhiyun  * or:
117*4882a593Smuzhiyun  *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
118*4882a593Smuzhiyun  */
119*4882a593Smuzhiyun #define FEC_OUT_PAD_CTRL	0
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	static const iomux_v3_cfg_t fec_pads[] = {
122*4882a593Smuzhiyun 		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
123*4882a593Smuzhiyun 		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
124*4882a593Smuzhiyun 		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
125*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
126*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
127*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
128*4882a593Smuzhiyun 		MX25_PAD_FEC_MDIO__FEC_MDIO,
129*4882a593Smuzhiyun 		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
130*4882a593Smuzhiyun 		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 		MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
133*4882a593Smuzhiyun 		MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
134*4882a593Smuzhiyun 	};
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	/* assert PHY reset (low) */
139*4882a593Smuzhiyun 	gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	udelay(5000);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/* deassert PHY reset */
144*4882a593Smuzhiyun 	gpio_set_value(IMX_GPIO_NR(3, 16), 1);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	udelay(5000);
147*4882a593Smuzhiyun #endif
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	e = env_get("gs_base_board");
150*4882a593Smuzhiyun 	if (e != NULL) {
151*4882a593Smuzhiyun 		if (strcmp(e, "G283") == 0) {
152*4882a593Smuzhiyun 			int key = gpio_get_value(IMX_GPIO_NR(2, 29));
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 			if (key) {
155*4882a593Smuzhiyun 				/* Switch on both LEDs to inidcate boot mode */
156*4882a593Smuzhiyun 				gpio_set_value(IMX_GPIO_NR(1, 29), 0);
157*4882a593Smuzhiyun 				gpio_set_value(IMX_GPIO_NR(4, 21), 0);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 				env_set("preboot", "run gs_slow_boot");
160*4882a593Smuzhiyun 			} else
161*4882a593Smuzhiyun 				env_set("preboot", "run gs_fast_boot");
162*4882a593Smuzhiyun 		}
163*4882a593Smuzhiyun 	}
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	return 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
dram_init(void)168*4882a593Smuzhiyun int dram_init(void)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	/* dram_init must store complete ramsize in gd->ram_size */
171*4882a593Smuzhiyun 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
172*4882a593Smuzhiyun 				PHYS_SDRAM_SIZE);
173*4882a593Smuzhiyun 	return 0;
174*4882a593Smuzhiyun }
175