1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Matthias Weisser <weisserm@arcor.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2009 DENX Software Engineering 6*4882a593Smuzhiyun * Author: John Rigby <jrigby@gmail.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on U-Boot and RedBoot sources for several different i.mx 9*4882a593Smuzhiyun * platforms. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#include <asm/macro.h> 15*4882a593Smuzhiyun#include <asm/arch/macro.h> 16*4882a593Smuzhiyun#include <asm/arch/imx-regs.h> 17*4882a593Smuzhiyun#include <generated/asm-offsets.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/* 20*4882a593Smuzhiyun * clocks 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun.macro init_clocks 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* disable clock output */ 25*4882a593Smuzhiyun write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 26*4882a593Smuzhiyun write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * enable all implemented clocks in all three 30*4882a593Smuzhiyun * clock control registers 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff 33*4882a593Smuzhiyun write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff 34*4882a593Smuzhiyun write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Devide NAND clock by 32 */ 37*4882a593Smuzhiyun write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F 38*4882a593Smuzhiyun.endm 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun/* 41*4882a593Smuzhiyun * sdram controller init 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun.macro init_lpddr 44*4882a593Smuzhiyun ldr r0, =IMX_ESDRAMC_BASE 45*4882a593Smuzhiyun ldr r2, =IMX_SDRAM_BANK0_BASE 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * reset SDRAM controller 49*4882a593Smuzhiyun * then wait for initialization to complete 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun ldr r1, =(1 << 1) | (1 << 2) 52*4882a593Smuzhiyun str r1, [r0, #ESDRAMC_ESDMISC] 53*4882a593Smuzhiyun1: ldr r3, [r0, #ESDRAMC_ESDMISC] 54*4882a593Smuzhiyun tst r3, #(1 << 31) 55*4882a593Smuzhiyun beq 1b 56*4882a593Smuzhiyun ldr r1, =(1 << 2) 57*4882a593Smuzhiyun str r1, [r0, #ESDRAMC_ESDMISC] 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ldr r1, =0x002a7420 60*4882a593Smuzhiyun str r1, [r0, #ESDRAMC_ESDCFG0] 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* control | precharge */ 63*4882a593Smuzhiyun ldr r1, =0x92216008 64*4882a593Smuzhiyun str r1, [r0, #ESDRAMC_ESDCTL0] 65*4882a593Smuzhiyun /* dram command encoded in address */ 66*4882a593Smuzhiyun str r1, [r2, #0x400] 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* auto refresh */ 69*4882a593Smuzhiyun ldr r1, =0xa2216008 70*4882a593Smuzhiyun str r1, [r0, #ESDRAMC_ESDCTL0] 71*4882a593Smuzhiyun /* read dram twice to auto refresh */ 72*4882a593Smuzhiyun ldr r3, [r2] 73*4882a593Smuzhiyun ldr r3, [r2] 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* control | load mode */ 76*4882a593Smuzhiyun ldr r1, =0xb2216008 77*4882a593Smuzhiyun str r1, [r0, #ESDRAMC_ESDCTL0] 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* mode register of lpddram */ 80*4882a593Smuzhiyun strb r1, [r2, #0x33] 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* extended mode register of lpddrram */ 83*4882a593Smuzhiyun ldr r2, =0x81000000 84*4882a593Smuzhiyun strb r1, [r2] 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* control | normal */ 87*4882a593Smuzhiyun ldr r1, =0x82216008 88*4882a593Smuzhiyun str r1, [r0, #ESDRAMC_ESDCTL0] 89*4882a593Smuzhiyun.endm 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun.globl lowlevel_init 92*4882a593Smuzhiyunlowlevel_init: 93*4882a593Smuzhiyun init_aips 94*4882a593Smuzhiyun init_max 95*4882a593Smuzhiyun init_clocks 96*4882a593Smuzhiyun init_lpddr 97*4882a593Smuzhiyun mov pc, lr 98