1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Board-specific early ddr/sdram init. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun.equ PPMCR0, 0xfc04002d 10*4882a593Smuzhiyun.equ MSCR_SDRAMC, 0xec094060 11*4882a593Smuzhiyun.equ MISCCR2, 0xec09001a 12*4882a593Smuzhiyun.equ DDR_RCR, 0xfc0b8180 13*4882a593Smuzhiyun.equ DDR_PADCR, 0xfc0b81ac 14*4882a593Smuzhiyun.equ DDR_CR00, 0xfc0b8000 15*4882a593Smuzhiyun.equ DDR_CR06, 0xfc0b8018 16*4882a593Smuzhiyun.equ DDR_CR09, 0xfc0b8024 17*4882a593Smuzhiyun.equ DDR_CR40, 0xfc0b80a0 18*4882a593Smuzhiyun.equ DDR_CR45, 0xfc0b80b4 19*4882a593Smuzhiyun.equ DDR_CR56, 0xfc0b80e0 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun.global sbf_dram_init 22*4882a593Smuzhiyun.text 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunsbf_dram_init: 25*4882a593Smuzhiyun /* CD46 = DDR on */ 26*4882a593Smuzhiyun move.l #PPMCR0, %a1 27*4882a593Smuzhiyun move.b #46, (%a1) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* stmark 2, max drive strength */ 30*4882a593Smuzhiyun move.l #MSCR_SDRAMC, %a1 31*4882a593Smuzhiyun move.b #1, (%a1) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * use cpu clock, seems more realiable 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * DDR2 clock is serviced from DDR controller as input clock / 2 37*4882a593Smuzhiyun * so, if clock comes from 38*4882a593Smuzhiyun * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured) 39*4882a593Smuzhiyun * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured) 40*4882a593Smuzhiyun * 41*4882a593Smuzhiyun * . 42*4882a593Smuzhiyun * / \ DDR2 can't be clocked lower than 125Mhz 43*4882a593Smuzhiyun * / ! \ DDR2 init must pass further i/dcache enable test 44*4882a593Smuzhiyun * /_____\ 45*4882a593Smuzhiyun * WARNING 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* cpu / 2 = 125 Mhz for 480 Mhz pll */ 49*4882a593Smuzhiyun move.l #MISCCR2, %a1 50*4882a593Smuzhiyun move.w #0xa01d, (%a1) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* DDR force sw reset settings */ 53*4882a593Smuzhiyun move.l #DDR_RCR, %a1 54*4882a593Smuzhiyun move.l #0x00000000, (%a1) 55*4882a593Smuzhiyun move.l #0x40000000, (%a1) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good, 59*4882a593Smuzhiyun * 500/700 mV are ok 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun move.l #DDR_PADCR, %a1 62*4882a593Smuzhiyun move.l #0x01030203, (%a1) /* as freescale tower */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun move.l #DDR_CR00, %a1 65*4882a593Smuzhiyun move.l #0x01010101, (%a1)+ /* 0x00 */ 66*4882a593Smuzhiyun move.l #0x00000101, (%a1)+ /* 0x04 */ 67*4882a593Smuzhiyun move.l #0x01010100, (%a1)+ /* 0x08 */ 68*4882a593Smuzhiyun move.l #0x01010000, (%a1)+ /* 0x0C */ 69*4882a593Smuzhiyun move.l #0x00010101, (%a1)+ /* 0x10 */ 70*4882a593Smuzhiyun move.l #DDR_CR06, %a1 71*4882a593Smuzhiyun move.l #0x00010100, (%a1)+ /* 0x18 */ 72*4882a593Smuzhiyun move.l #0x00000001, (%a1)+ /* 0x1C */ 73*4882a593Smuzhiyun move.l #0x01000001, (%a1)+ /* 0x20 */ 74*4882a593Smuzhiyun move.l #0x00000100, (%a1)+ /* 0x24 */ 75*4882a593Smuzhiyun move.l #0x00010001, (%a1)+ /* 0x28 */ 76*4882a593Smuzhiyun move.l #0x00000200, (%a1)+ /* 0x2C */ 77*4882a593Smuzhiyun move.l #0x01000002, (%a1)+ /* 0x30 */ 78*4882a593Smuzhiyun move.l #0x00000000, (%a1)+ /* 0x34 */ 79*4882a593Smuzhiyun move.l #0x00000100, (%a1)+ /* 0x38 */ 80*4882a593Smuzhiyun move.l #0x02000100, (%a1)+ /* 0x3C */ 81*4882a593Smuzhiyun move.l #0x02000407, (%a1)+ /* 0x40 */ 82*4882a593Smuzhiyun move.l #0x02030007, (%a1)+ /* 0x44 */ 83*4882a593Smuzhiyun move.l #0x02000100, (%a1)+ /* 0x48 */ 84*4882a593Smuzhiyun move.l #0x0A030203, (%a1)+ /* 0x4C */ 85*4882a593Smuzhiyun move.l #0x00020708, (%a1)+ /* 0x50 */ 86*4882a593Smuzhiyun move.l #0x00050008, (%a1)+ /* 0x54 */ 87*4882a593Smuzhiyun move.l #0x04030002, (%a1)+ /* 0x58 */ 88*4882a593Smuzhiyun move.l #0x00000004, (%a1)+ /* 0x5C */ 89*4882a593Smuzhiyun move.l #0x020A0000, (%a1)+ /* 0x60 */ 90*4882a593Smuzhiyun move.l #0x0C00000E, (%a1)+ /* 0x64 */ 91*4882a593Smuzhiyun move.l #0x00002004, (%a1)+ /* 0x68 */ 92*4882a593Smuzhiyun move.l #0x00000000, (%a1)+ /* 0x6C */ 93*4882a593Smuzhiyun move.l #0x00100010, (%a1)+ /* 0x70 */ 94*4882a593Smuzhiyun move.l #0x00100010, (%a1)+ /* 0x74 */ 95*4882a593Smuzhiyun move.l #0x00000000, (%a1)+ /* 0x78 */ 96*4882a593Smuzhiyun move.l #0x07990000, (%a1)+ /* 0x7C */ 97*4882a593Smuzhiyun move.l #DDR_CR40, %a1 98*4882a593Smuzhiyun move.l #0x00000000, (%a1)+ /* 0xA0 */ 99*4882a593Smuzhiyun move.l #0x00C80064, (%a1)+ /* 0xA4 */ 100*4882a593Smuzhiyun move.l #0x44520002, (%a1)+ /* 0xA8 */ 101*4882a593Smuzhiyun move.l #0x00C80023, (%a1)+ /* 0xAC */ 102*4882a593Smuzhiyun move.l #DDR_CR45, %a1 103*4882a593Smuzhiyun move.l #0x0000C350, (%a1) /* 0xB4 */ 104*4882a593Smuzhiyun move.l #DDR_CR56, %a1 105*4882a593Smuzhiyun move.l #0x04000000, (%a1)+ /* 0xE0 */ 106*4882a593Smuzhiyun move.l #0x03000304, (%a1)+ /* 0xE4 */ 107*4882a593Smuzhiyun move.l #0x40040000, (%a1)+ /* 0xE8 */ 108*4882a593Smuzhiyun move.l #0xC0004004, (%a1)+ /* 0xEC */ 109*4882a593Smuzhiyun move.l #0x0642C000, (%a1)+ /* 0xF0 */ 110*4882a593Smuzhiyun move.l #0x00000642, (%a1)+ /* 0xF4 */ 111*4882a593Smuzhiyun move.l #DDR_CR09, %a1 112*4882a593Smuzhiyun tpf 113*4882a593Smuzhiyun move.l #0x01000100, (%a1) /* 0x24 */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun move.l #0x2000, %d1 116*4882a593Smuzhiyun bsr asm_delay 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun rts 120