1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dwmmc.h>
9*4882a593Smuzhiyun #include <malloc.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
14*4882a593Smuzhiyun #define CREG_PAE (CREG_BASE + 0x180)
15*4882a593Smuzhiyun #define CREG_PAE_UPDATE (CREG_BASE + 0x194)
16*4882a593Smuzhiyun #define CREG_CPU_START (CREG_BASE + 0x400)
17*4882a593Smuzhiyun
board_early_init_f(void)18*4882a593Smuzhiyun int board_early_init_f(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun /* In current chip PAE support for DMA is broken, disabling it. */
21*4882a593Smuzhiyun writel(0, (void __iomem *) CREG_PAE);
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* Really apply settings made above */
24*4882a593Smuzhiyun writel(1, (void __iomem *) CREG_PAE_UPDATE);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
board_mmc_init(bd_t * bis)29*4882a593Smuzhiyun int board_mmc_init(bd_t *bis)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct dwmci_host *host = NULL;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun host = malloc(sizeof(struct dwmci_host));
34*4882a593Smuzhiyun if (!host) {
35*4882a593Smuzhiyun printf("dwmci_host malloc fail!\n");
36*4882a593Smuzhiyun return 1;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun memset(host, 0, sizeof(struct dwmci_host));
40*4882a593Smuzhiyun host->name = "Synopsys Mobile storage";
41*4882a593Smuzhiyun host->ioaddr = (void *)ARC_DWMMC_BASE;
42*4882a593Smuzhiyun host->buswidth = 4;
43*4882a593Smuzhiyun host->dev_index = 0;
44*4882a593Smuzhiyun host->bus_hz = 100000000;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun add_dwmci(host, host->bus_hz / 2, 400000);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define RESET_VECTOR_ADDR 0x0
52*4882a593Smuzhiyun
smp_set_core_boot_addr(unsigned long addr,int corenr)53*4882a593Smuzhiyun void smp_set_core_boot_addr(unsigned long addr, int corenr)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun /* All cores have reset vector pointing to 0 */
56*4882a593Smuzhiyun writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Make sure other cores see written value in memory */
59*4882a593Smuzhiyun flush_dcache_all();
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
smp_kick_all_cpus(void)62*4882a593Smuzhiyun void smp_kick_all_cpus(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun #define BITS_START_CORE1 1
65*4882a593Smuzhiyun #define BITS_START_CORE2 2
66*4882a593Smuzhiyun #define BITS_START_CORE3 3
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun int cmd = readl((void __iomem *)CREG_CPU_START);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun cmd |= (1 << BITS_START_CORE1) |
71*4882a593Smuzhiyun (1 << BITS_START_CORE2) |
72*4882a593Smuzhiyun (1 << BITS_START_CORE3);
73*4882a593Smuzhiyun writel(cmd, (void __iomem *)CREG_CPU_START);
74*4882a593Smuzhiyun }
75