1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <dwmmc.h> 9*4882a593Smuzhiyun #include <malloc.h> 10*4882a593Smuzhiyun #include <asm/arcregs.h> 11*4882a593Smuzhiyun #include "axs10x.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 14*4882a593Smuzhiyun board_mmc_init(bd_t * bis)15*4882a593Smuzhiyunint board_mmc_init(bd_t *bis) 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun struct dwmci_host *host = NULL; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun host = malloc(sizeof(struct dwmci_host)); 20*4882a593Smuzhiyun if (!host) { 21*4882a593Smuzhiyun printf("dwmci_host malloc fail!\n"); 22*4882a593Smuzhiyun return 1; 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun memset(host, 0, sizeof(struct dwmci_host)); 26*4882a593Smuzhiyun host->name = "Synopsys Mobile storage"; 27*4882a593Smuzhiyun host->ioaddr = (void *)ARC_DWMMC_BASE; 28*4882a593Smuzhiyun host->buswidth = 4; 29*4882a593Smuzhiyun host->dev_index = 0; 30*4882a593Smuzhiyun host->bus_hz = 50000000; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun add_dwmci(host, host->bus_hz / 2, 400000); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun return 0; 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AXS_MB_CREG 0xE0011000 38*4882a593Smuzhiyun board_early_init_f(void)39*4882a593Smuzhiyunint board_early_init_f(void) 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28)) 42*4882a593Smuzhiyun gd->board_type = AXS_MB_V3; 43*4882a593Smuzhiyun else 44*4882a593Smuzhiyun gd->board_type = AXS_MB_V2; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun return 0; 47*4882a593Smuzhiyun } 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #ifdef CONFIG_ISA_ARCV2 50*4882a593Smuzhiyun #define RESET_VECTOR_ADDR 0x0 51*4882a593Smuzhiyun smp_set_core_boot_addr(unsigned long addr,int corenr)52*4882a593Smuzhiyunvoid smp_set_core_boot_addr(unsigned long addr, int corenr) 53*4882a593Smuzhiyun { 54*4882a593Smuzhiyun /* All cores have reset vector pointing to 0 */ 55*4882a593Smuzhiyun writel(addr, (void __iomem *)RESET_VECTOR_ADDR); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Make sure other cores see written value in memory */ 58*4882a593Smuzhiyun flush_dcache_all(); 59*4882a593Smuzhiyun } 60*4882a593Smuzhiyun smp_kick_all_cpus(void)61*4882a593Smuzhiyunvoid smp_kick_all_cpus(void) 62*4882a593Smuzhiyun { 63*4882a593Smuzhiyun /* CPU start CREG */ 64*4882a593Smuzhiyun #define AXC003_CREG_CPU_START 0xF0001400 65*4882a593Smuzhiyun /* Bits positions in CPU start CREG */ 66*4882a593Smuzhiyun #define BITS_START 0 67*4882a593Smuzhiyun #define BITS_START_MODE 4 68*4882a593Smuzhiyun #define BITS_CORE_SEL 9 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * In axs103 v1.1 START bits semantics has changed quite a bit. 72*4882a593Smuzhiyun * We used to have a generic START bit for all cores selected by CORE_SEL mask. 73*4882a593Smuzhiyun * But now we don't touch CORE_SEL at all because we have a dedicated START bit 74*4882a593Smuzhiyun * for each core: 75*4882a593Smuzhiyun * bit 0: Core 0 (master) 76*4882a593Smuzhiyun * bit 1: Core 1 (slave) 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #define BITS_START_CORE1 1 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define ARCVER_HS38_3_0 0x53 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff; 83*4882a593Smuzhiyun int cmd = readl((void __iomem *)AXC003_CREG_CPU_START); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun if (core_family < ARCVER_HS38_3_0) { 86*4882a593Smuzhiyun cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START); 87*4882a593Smuzhiyun cmd &= ~(1 << BITS_START_MODE); 88*4882a593Smuzhiyun } else { 89*4882a593Smuzhiyun cmd |= (1 << BITS_START_CORE1); 90*4882a593Smuzhiyun } 91*4882a593Smuzhiyun writel(cmd, (void __iomem *)AXC003_CREG_CPU_START); 92*4882a593Smuzhiyun } 93*4882a593Smuzhiyun #endif 94