1*4882a593Smuzhiyun #include <common.h>
2*4882a593Smuzhiyun #include <asm/arch/dram.h>
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun static struct dram_para dram_para = {
5*4882a593Smuzhiyun .clock = CONFIG_DRAM_CLK,
6*4882a593Smuzhiyun .type = 3,
7*4882a593Smuzhiyun .rank_num = 1,
8*4882a593Smuzhiyun .density = 0,
9*4882a593Smuzhiyun .io_width = 0,
10*4882a593Smuzhiyun .bus_width = 0,
11*4882a593Smuzhiyun .zq = CONFIG_DRAM_ZQ,
12*4882a593Smuzhiyun .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
13*4882a593Smuzhiyun .size = 0,
14*4882a593Smuzhiyun #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
15*4882a593Smuzhiyun .cas = 6,
16*4882a593Smuzhiyun .tpr0 = 0x30926692,
17*4882a593Smuzhiyun .tpr1 = 0x1090,
18*4882a593Smuzhiyun .tpr2 = 0x1a0c8,
19*4882a593Smuzhiyun .emr2 = 0,
20*4882a593Smuzhiyun #else
21*4882a593Smuzhiyun # include "dram_timings_sun4i.h"
22*4882a593Smuzhiyun .active_windowing = 1,
23*4882a593Smuzhiyun #endif
24*4882a593Smuzhiyun .tpr3 = CONFIG_DRAM_TPR3,
25*4882a593Smuzhiyun .tpr4 = 0,
26*4882a593Smuzhiyun .tpr5 = 0,
27*4882a593Smuzhiyun .emr1 = CONFIG_DRAM_EMR1,
28*4882a593Smuzhiyun .emr3 = 0,
29*4882a593Smuzhiyun .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
sunxi_dram_init(void)32*4882a593Smuzhiyun unsigned long sunxi_dram_init(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun return dramc_init(&dram_para);
35*4882a593Smuzhiyun }
36