1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014
3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <miiphy.h>
11*4882a593Smuzhiyun #include <asm/arch/stv0991_periph.h>
12*4882a593Smuzhiyun #include <asm/arch/stv0991_defs.h>
13*4882a593Smuzhiyun #include <asm/arch/hardware.h>
14*4882a593Smuzhiyun #include <asm/arch/gpio.h>
15*4882a593Smuzhiyun #include <netdev.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <dm/platform_data/serial_pl01x.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct gpio_regs *const gpioa_regs =
22*4882a593Smuzhiyun (struct gpio_regs *) GPIOA_BASE_ADDR;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #ifndef CONFIG_OF_CONTROL
25*4882a593Smuzhiyun static const struct pl01x_serial_platdata serial_platdata = {
26*4882a593Smuzhiyun .base = 0x80406000,
27*4882a593Smuzhiyun .type = TYPE_PL011,
28*4882a593Smuzhiyun .clock = 2700 * 1000,
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun U_BOOT_DEVICE(stv09911_serials) = {
32*4882a593Smuzhiyun .name = "serial_pl01x",
33*4882a593Smuzhiyun .platdata = &serial_platdata,
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #ifdef CONFIG_SHOW_BOOT_PROGRESS
show_boot_progress(int progress)38*4882a593Smuzhiyun void show_boot_progress(int progress)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun printf("%i\n", progress);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun
enable_eth_phy(void)44*4882a593Smuzhiyun void enable_eth_phy(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun /* Set GPIOA_06 pad HIGH (Appli board)*/
47*4882a593Smuzhiyun writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
48*4882a593Smuzhiyun writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
49*4882a593Smuzhiyun }
board_eth_enable(void)50*4882a593Smuzhiyun int board_eth_enable(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
53*4882a593Smuzhiyun clock_setup(ETH_CLOCK_CFG);
54*4882a593Smuzhiyun enable_eth_phy();
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
board_qspi_enable(void)58*4882a593Smuzhiyun int board_qspi_enable(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun stv0991_pinmux_config(QSPI_CS_CLK_PAD);
61*4882a593Smuzhiyun clock_setup(QSPI_CLOCK_CFG);
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * Miscellaneous platform dependent initialisations
67*4882a593Smuzhiyun */
board_init(void)68*4882a593Smuzhiyun int board_init(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun board_eth_enable();
71*4882a593Smuzhiyun board_qspi_enable();
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
board_uart_init(void)75*4882a593Smuzhiyun int board_uart_init(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun stv0991_pinmux_config(UART_GPIOC_30_31);
78*4882a593Smuzhiyun clock_setup(UART_CLOCK_CFG);
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)83*4882a593Smuzhiyun int board_early_init_f(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun board_uart_init();
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun #endif
89*4882a593Smuzhiyun
dram_init(void)90*4882a593Smuzhiyun int dram_init(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun gd->ram_size = PHYS_SDRAM_1_SIZE;
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
dram_init_banksize(void)96*4882a593Smuzhiyun int dram_init_banksize(void)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
99*4882a593Smuzhiyun gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET
board_eth_init(bd_t * bis)105*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun int ret = 0;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #if defined(CONFIG_ETH_DESIGNWARE)
110*4882a593Smuzhiyun u32 interface = PHY_INTERFACE_MODE_MII;
111*4882a593Smuzhiyun if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
112*4882a593Smuzhiyun ret++;
113*4882a593Smuzhiyun #endif
114*4882a593Smuzhiyun return ret;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun #endif
117