1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Ryan Chen, ST Micoelectronics, ryan.chen@st.com. 4*4882a593Smuzhiyun * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #include <miiphy.h> 11*4882a593Smuzhiyun #include <netdev.h> 12*4882a593Smuzhiyun #include <nand.h> 13*4882a593Smuzhiyun #include <asm/io.h> 14*4882a593Smuzhiyun #include <linux/mtd/fsmc_nand.h> 15*4882a593Smuzhiyun #include <asm/mach-types.h> 16*4882a593Smuzhiyun #include <asm/arch/hardware.h> 17*4882a593Smuzhiyun #include <asm/arch/spr_defs.h> 18*4882a593Smuzhiyun #include <asm/arch/spr_misc.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define PLGPIO_SEL_36 0xb3000028 21*4882a593Smuzhiyun #define PLGPIO_IO_36 0xb3000038 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; 24*4882a593Smuzhiyun spear_phy_reset(void)25*4882a593Smuzhiyunstatic void spear_phy_reset(void) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun writel(0x10, PLGPIO_IO_36); 28*4882a593Smuzhiyun writel(0x10, PLGPIO_SEL_36); 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun board_init(void)31*4882a593Smuzhiyunint board_init(void) 32*4882a593Smuzhiyun { 33*4882a593Smuzhiyun spear_phy_reset(); 34*4882a593Smuzhiyun return spear_board_init(MACH_TYPE_SPEAR320); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * board_nand_init - Board specific NAND initialization 39*4882a593Smuzhiyun * @nand: mtd private chip structure 40*4882a593Smuzhiyun * 41*4882a593Smuzhiyun * Called by nand_init_chip to initialize the board specific functions 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun board_nand_init()44*4882a593Smuzhiyunvoid board_nand_init() 45*4882a593Smuzhiyun { 46*4882a593Smuzhiyun struct misc_regs *const misc_regs_p = 47*4882a593Smuzhiyun (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 48*4882a593Smuzhiyun struct nand_chip *nand = &nand_chip[0]; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #if defined(CONFIG_NAND_FSMC) 51*4882a593Smuzhiyun if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == 52*4882a593Smuzhiyun MISC_SOCCFG30) || 53*4882a593Smuzhiyun ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == 54*4882a593Smuzhiyun MISC_SOCCFG31)) { 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun fsmc_nand_init(nand); 57*4882a593Smuzhiyun } 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun return; 61*4882a593Smuzhiyun } 62*4882a593Smuzhiyun board_eth_init(bd_t * bis)63*4882a593Smuzhiyunint board_eth_init(bd_t *bis) 64*4882a593Smuzhiyun { 65*4882a593Smuzhiyun int ret = 0; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #if defined(CONFIG_ETH_DESIGNWARE) 68*4882a593Smuzhiyun u32 interface = PHY_INTERFACE_MODE_MII; 69*4882a593Smuzhiyun if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) 70*4882a593Smuzhiyun ret++; 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun #if defined(CONFIG_MACB) 73*4882a593Smuzhiyun if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, 74*4882a593Smuzhiyun CONFIG_MACB0_PHY) >= 0) 75*4882a593Smuzhiyun ret++; 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun return ret; 78*4882a593Smuzhiyun } 79