1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 3*4882a593Smuzhiyun * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2000 8*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <common.h> 14*4882a593Smuzhiyun #include <asm/mmu.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 17*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 19*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 20*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 21*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 22*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 24*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 29*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * TLB 1: 64M Non-cacheable, guarded 34*4882a593Smuzhiyun * 0xfc000000 64M FLASH 35*4882a593Smuzhiyun * Out of reset this entry is only 4K. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, 38*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_64M, 1), 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * TLB 2: 256M Non-cacheable, guarded 43*4882a593Smuzhiyun * 0x80000000 256M PCI1 MEM First half 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, 46*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 47*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_256M, 1), 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * TLB 3: 256M Non-cacheable, guarded 51*4882a593Smuzhiyun * 0x90000000 256M PCI1 MEM Second half 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, 54*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_256M, 1), 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #if defined(CONFIG_SYS_FPGA_BASE) 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * TLB 4: 1M Non-cacheable, guarded 60*4882a593Smuzhiyun * 0xc0000000 1M FPGA and NAND 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, 63*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_1M, 1), 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * TLB 5: 64M Non-cacheable, guarded 69*4882a593Smuzhiyun * 0xc8000000 16M LIME GDC framebuffer 70*4882a593Smuzhiyun * 0xc9fc0000 256K LIME GDC MMIO 71*4882a593Smuzhiyun * (0xcbfc0000 256K LIME GDC MMIO) 72*4882a593Smuzhiyun * MMIO is relocatable and could be at 0xcbfc0000 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, 75*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 76*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_64M, 1), 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * TLB 6: 64M Non-cacheable, guarded 80*4882a593Smuzhiyun * 0xe000_0000 1M CCSRBAR 81*4882a593Smuzhiyun * 0xe200_0000 16M PCI1 IO 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 84*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 85*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_64M, 1), 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #if !defined(CONFIG_SPD_EEPROM) 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * TLB 7+8: 512M DDR, cache disabled (needed for memory test) 90*4882a593Smuzhiyun * 0x00000000 512M DDR System memory 91*4882a593Smuzhiyun * Without SPD EEPROM configured DDR, this must be setup manually. 92*4882a593Smuzhiyun * Make sure the TLB count at the top of this table is correct. 93*4882a593Smuzhiyun * Likely it needs to be increased by two for these entries. 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 96*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97*4882a593Smuzhiyun 0, 7, BOOKE_PAGESZ_256M, 1), 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 100*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 101*4882a593Smuzhiyun 0, 8, BOOKE_PAGESZ_256M, 1), 102*4882a593Smuzhiyun #endif 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 106