1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 3*4882a593Smuzhiyun * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/processor.h> 10*4882a593Smuzhiyun #include <asm/immap_85xx.h> 11*4882a593Smuzhiyun #include <fsl_ddr_sdram.h> 12*4882a593Smuzhiyun #include <asm/processor.h> 13*4882a593Smuzhiyun #include <asm/mmu.h> 14*4882a593Smuzhiyun #include <spd_sdram.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #if !defined(CONFIG_SPD_EEPROM) 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Autodetect onboard DDR SDRAM on 85xx platforms 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * NOTE: Some of the hardcoded values are hardware dependant, 22*4882a593Smuzhiyun * so this should be extended for other future boards 23*4882a593Smuzhiyun * using this routine! 24*4882a593Smuzhiyun */ fixed_sdram(void)25*4882a593Smuzhiyunphys_size_t fixed_sdram(void) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun struct ccsr_ddr __iomem *ddr = 28*4882a593Smuzhiyun (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * Disable memory controller. 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun ddr->cs0_config = 0; 34*4882a593Smuzhiyun ddr->sdram_cfg = 0; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 37*4882a593Smuzhiyun ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 38*4882a593Smuzhiyun ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 39*4882a593Smuzhiyun ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 40*4882a593Smuzhiyun ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 41*4882a593Smuzhiyun ddr->sdram_mode = CONFIG_SYS_DDR_MODE; 42*4882a593Smuzhiyun ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 43*4882a593Smuzhiyun ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; 44*4882a593Smuzhiyun ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun asm ("sync;isync;msync"); 47*4882a593Smuzhiyun udelay(1000); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; 50*4882a593Smuzhiyun asm ("sync; isync; msync"); 51*4882a593Smuzhiyun udelay(1000); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * OK, size detected -> all done 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun return CONFIG_SYS_SDRAM_SIZE<<20; 58*4882a593Smuzhiyun } 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun return 0; /* nothing found ! */ 61*4882a593Smuzhiyun } 62*4882a593Smuzhiyun #endif 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #if defined(CONFIG_SYS_DRAM_TEST) testdram(void)65*4882a593Smuzhiyunint testdram (void) 66*4882a593Smuzhiyun { 67*4882a593Smuzhiyun uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 68*4882a593Smuzhiyun uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 69*4882a593Smuzhiyun uint *p; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun printf ("SDRAM test phase 1:\n"); 72*4882a593Smuzhiyun for (p = pstart; p < pend; p++) 73*4882a593Smuzhiyun *p = 0xaaaaaaaa; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun for (p = pstart; p < pend; p++) { 76*4882a593Smuzhiyun if (*p != 0xaaaaaaaa) { 77*4882a593Smuzhiyun printf ("SDRAM test fails at: %08x\n", (uint) p); 78*4882a593Smuzhiyun return 1; 79*4882a593Smuzhiyun } 80*4882a593Smuzhiyun } 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun printf ("SDRAM test phase 2:\n"); 83*4882a593Smuzhiyun for (p = pstart; p < pend; p++) 84*4882a593Smuzhiyun *p = 0x55555555; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun for (p = pstart; p < pend; p++) { 87*4882a593Smuzhiyun if (*p != 0x55555555) { 88*4882a593Smuzhiyun printf ("SDRAM test fails at: %08x\n", (uint) p); 89*4882a593Smuzhiyun return 1; 90*4882a593Smuzhiyun } 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun printf ("SDRAM test passed.\n"); 94*4882a593Smuzhiyun return 0; 95*4882a593Smuzhiyun } 96*4882a593Smuzhiyun #endif 97