xref: /OK3568_Linux_fs/u-boot/board/socrates/law.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2008
3*4882a593Smuzhiyun  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2008 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * (C) Copyright 2000
8*4882a593Smuzhiyun  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <asm/fsl_law.h>
15*4882a593Smuzhiyun #include <asm/mmu.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun  * LAW(Local Access Window) configuration:
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  * 0x0000_0000	   0x2fff_ffff	   DDR			   512M
21*4882a593Smuzhiyun  * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
22*4882a593Smuzhiyun  * 0xc000_0000	   0xc00f_ffff	   FPGA			   1M
23*4882a593Smuzhiyun  * 0xc800_0000	   0xcbff_ffff	   LIME			   64M
24*4882a593Smuzhiyun  * 0xe000_0000	   0xe00f_ffff	   CCSR			   1M (mapped by CCSRBAR)
25*4882a593Smuzhiyun  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
26*4882a593Smuzhiyun  * 0xfc00_0000	   0xffff_ffff	   FLASH		   64M
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  * Notes:
29*4882a593Smuzhiyun  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
30*4882a593Smuzhiyun  *    If flash is 8M at default position (last 8M), no LAW needed.
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun struct law_entry law_table[] = {
34*4882a593Smuzhiyun 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
35*4882a593Smuzhiyun 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
36*4882a593Smuzhiyun 	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
37*4882a593Smuzhiyun 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
38*4882a593Smuzhiyun #if defined(CONFIG_SYS_FPGA_BASE)
39*4882a593Smuzhiyun 	SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
40*4882a593Smuzhiyun #endif
41*4882a593Smuzhiyun 	SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun int num_law_entries = ARRAY_SIZE(law_table);
45