1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 Siemens Schweiz AG 3*4882a593Smuzhiyun * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Based on: 6*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef PMIC_H 11*4882a593Smuzhiyun #define PMIC_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * The PMIC on this board is a TPS65910. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define PMIC_SR_I2C_ADDR 0x12 18*4882a593Smuzhiyun #define PMIC_CTRL_I2C_ADDR 0x2D 19*4882a593Smuzhiyun /* PMIC Register offsets */ 20*4882a593Smuzhiyun #define PMIC_VDD1_REG 0x21 21*4882a593Smuzhiyun #define PMIC_VDD1_OP_REG 0x22 22*4882a593Smuzhiyun #define PMIC_VDD2_REG 0x24 23*4882a593Smuzhiyun #define PMIC_VDD2_OP_REG 0x25 24*4882a593Smuzhiyun #define PMIC_DEVCTRL_REG 0x3f 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ 27*4882a593Smuzhiyun #define PMIC_VGAIN_SEL_MASK (0x3 << 6) 28*4882a593Smuzhiyun #define PMIC_ILMAX_MASK (0x1 << 5) 29*4882a593Smuzhiyun #define PMIC_TSTEP_MASK (0x7 << 2) 30*4882a593Smuzhiyun #define PMIC_ST_MASK (0x3) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6) 33*4882a593Smuzhiyun #define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6) 34*4882a593Smuzhiyun #define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6) 35*4882a593Smuzhiyun #define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define PMIC_REG_ILMAX_1_0_A (0x0 << 5) 38*4882a593Smuzhiyun #define PMIC_REG_ILMAX_1_5_A (0x1 << 5) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define PMIC_REG_TSTEP_ (0x0 << 2) 41*4882a593Smuzhiyun #define PMIC_REG_TSTEP_12_5 (0x1 << 2) 42*4882a593Smuzhiyun #define PMIC_REG_TSTEP_9_4 (0x2 << 2) 43*4882a593Smuzhiyun #define PMIC_REG_TSTEP_7_5 (0x3 << 2) 44*4882a593Smuzhiyun #define PMIC_REG_TSTEP_6_25 (0x4 << 2) 45*4882a593Smuzhiyun #define PMIC_REG_TSTEP_4_7 (0x5 << 2) 46*4882a593Smuzhiyun #define PMIC_REG_TSTEP_3_12 (0x6 << 2) 47*4882a593Smuzhiyun #define PMIC_REG_TSTEP_2_5 (0x7 << 2) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define PMIC_REG_ST_OFF (0x0) 50*4882a593Smuzhiyun #define PMIC_REG_ST_ON_HI_POW (0x1) 51*4882a593Smuzhiyun #define PMIC_REG_ST_OFF_1 (0x2) 52*4882a593Smuzhiyun #define PMIC_REG_ST_ON_LOW_POW (0x3) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ 56*4882a593Smuzhiyun #define PMIC_OP_REG_SEL (0x7F) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PMIC_OP_REG_CMD_MASK (0x1 << 7) 59*4882a593Smuzhiyun #define PMIC_OP_REG_CMD_OP (0x0 << 7) 60*4882a593Smuzhiyun #define PMIC_OP_REG_CMD_SR (0x1 << 7) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define PMIC_OP_REG_SEL_MASK (0x7F) 63*4882a593Smuzhiyun #define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ 64*4882a593Smuzhiyun #define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Device control register . (DEVCTRL_REG) */ 67*4882a593Smuzhiyun #define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) 68*4882a593Smuzhiyun #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) 69*4882a593Smuzhiyun #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif 72