1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Copyright (C) 2015 ECA Sinters
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Fabio Estevam <fabio.estevam@freescale.com>
6*4882a593Smuzhiyun * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/arch/clock.h>
12*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
13*4882a593Smuzhiyun #include <asm/arch/iomux.h>
14*4882a593Smuzhiyun #include <asm/arch/mx6-pins.h>
15*4882a593Smuzhiyun #include <linux/errno.h>
16*4882a593Smuzhiyun #include <asm/gpio.h>
17*4882a593Smuzhiyun #include <asm/mach-imx/iomux-v3.h>
18*4882a593Smuzhiyun #include <asm/mach-imx/boot_mode.h>
19*4882a593Smuzhiyun #include <mmc.h>
20*4882a593Smuzhiyun #include <fsl_esdhc.h>
21*4882a593Smuzhiyun #include <miiphy.h>
22*4882a593Smuzhiyun #include <netdev.h>
23*4882a593Smuzhiyun #include <asm/arch/mxc_hdmi.h>
24*4882a593Smuzhiyun #include <asm/arch/crm_regs.h>
25*4882a593Smuzhiyun #include <linux/fb.h>
26*4882a593Smuzhiyun #include <ipu_pixfmt.h>
27*4882a593Smuzhiyun #include <asm/io.h>
28*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
29*4882a593Smuzhiyun #include <micrel.h>
30*4882a593Smuzhiyun #include <asm/mach-imx/mxc_i2c.h>
31*4882a593Smuzhiyun #include <i2c.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34*4882a593Smuzhiyun PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
35*4882a593Smuzhiyun PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static iomux_v3_cfg_t const uart2_pads[] = {
38*4882a593Smuzhiyun MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
39*4882a593Smuzhiyun MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
seco_mx6_setup_uart_iomux(void)42*4882a593Smuzhiyun void seco_mx6_setup_uart_iomux(void)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
48*4882a593Smuzhiyun PAD_CTL_SPEED_MED | \
49*4882a593Smuzhiyun PAD_CTL_DSE_40ohm | \
50*4882a593Smuzhiyun PAD_CTL_HYS)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static iomux_v3_cfg_t const enet_pads[] = {
53*4882a593Smuzhiyun MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
54*4882a593Smuzhiyun MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
55*4882a593Smuzhiyun MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
56*4882a593Smuzhiyun MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
57*4882a593Smuzhiyun MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
58*4882a593Smuzhiyun MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
59*4882a593Smuzhiyun MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
60*4882a593Smuzhiyun MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
61*4882a593Smuzhiyun MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
62*4882a593Smuzhiyun MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
63*4882a593Smuzhiyun MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
64*4882a593Smuzhiyun MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
65*4882a593Smuzhiyun MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
66*4882a593Smuzhiyun MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67*4882a593Smuzhiyun MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
seco_mx6_setup_enet_iomux(void)70*4882a593Smuzhiyun void seco_mx6_setup_enet_iomux(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
seco_mx6_rgmii_rework(struct phy_device * phydev)75*4882a593Smuzhiyun int seco_mx6_rgmii_rework(struct phy_device *phydev)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun /* control data pad skew - devaddr = 0x02, register = 0x04 */
78*4882a593Smuzhiyun ksz9031_phy_extended_write(phydev, 0x02,
79*4882a593Smuzhiyun MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
80*4882a593Smuzhiyun MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
81*4882a593Smuzhiyun /* rx data pad skew - devaddr = 0x02, register = 0x05 */
82*4882a593Smuzhiyun ksz9031_phy_extended_write(phydev, 0x02,
83*4882a593Smuzhiyun MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
84*4882a593Smuzhiyun MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
85*4882a593Smuzhiyun /* tx data pad skew - devaddr = 0x02, register = 0x05 */
86*4882a593Smuzhiyun ksz9031_phy_extended_write(phydev, 0x02,
87*4882a593Smuzhiyun MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
88*4882a593Smuzhiyun MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
91*4882a593Smuzhiyun ksz9031_phy_extended_write(phydev, 0x02,
92*4882a593Smuzhiyun MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
93*4882a593Smuzhiyun MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
94*4882a593Smuzhiyun return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
98*4882a593Smuzhiyun PAD_CTL_SPEED_LOW | \
99*4882a593Smuzhiyun PAD_CTL_DSE_80ohm | \
100*4882a593Smuzhiyun PAD_CTL_SRE_FAST | \
101*4882a593Smuzhiyun PAD_CTL_HYS)
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static iomux_v3_cfg_t const usdhc3_pads[] = {
104*4882a593Smuzhiyun MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105*4882a593Smuzhiyun MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106*4882a593Smuzhiyun MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107*4882a593Smuzhiyun MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108*4882a593Smuzhiyun MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109*4882a593Smuzhiyun MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static iomux_v3_cfg_t const usdhc4_pads[] = {
113*4882a593Smuzhiyun MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114*4882a593Smuzhiyun MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115*4882a593Smuzhiyun MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116*4882a593Smuzhiyun MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117*4882a593Smuzhiyun MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118*4882a593Smuzhiyun MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
seco_mx6_setup_usdhc_iomux(int id)121*4882a593Smuzhiyun void seco_mx6_setup_usdhc_iomux(int id)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun switch (id) {
124*4882a593Smuzhiyun case 3:
125*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
126*4882a593Smuzhiyun ARRAY_SIZE(usdhc3_pads));
127*4882a593Smuzhiyun break;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun case 4:
130*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(usdhc4_pads,
131*4882a593Smuzhiyun ARRAY_SIZE(usdhc4_pads));
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun default:
135*4882a593Smuzhiyun printf("Warning: invalid usdhc id (%d)\n", id);
136*4882a593Smuzhiyun break;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun }
139