1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SchulerControl GmbH, SC_SPS_1 module setup
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2012 Marek Vasut <marex@denx.de>
5*4882a593Smuzhiyun * on behalf of DENX Software Engineering GmbH
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <config.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/arch/iomux-mx28.h>
14*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
15*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
18*4882a593Smuzhiyun #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
19*4882a593Smuzhiyun #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
20*4882a593Smuzhiyun #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
21*4882a593Smuzhiyun #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun const iomux_cfg_t iomux_setup[] = {
24*4882a593Smuzhiyun /* -- Strick 3 -- */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* FEC Ethernet */
27*4882a593Smuzhiyun MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
28*4882a593Smuzhiyun MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
29*4882a593Smuzhiyun MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
30*4882a593Smuzhiyun MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
31*4882a593Smuzhiyun MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
32*4882a593Smuzhiyun MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
33*4882a593Smuzhiyun MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
34*4882a593Smuzhiyun MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
35*4882a593Smuzhiyun MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
36*4882a593Smuzhiyun MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
37*4882a593Smuzhiyun MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
38*4882a593Smuzhiyun MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* ENET INT */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
43*4882a593Smuzhiyun MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
44*4882a593Smuzhiyun MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* -- Strick 4 -- */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* EMI */
49*4882a593Smuzhiyun MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
50*4882a593Smuzhiyun MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
51*4882a593Smuzhiyun MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
52*4882a593Smuzhiyun MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
53*4882a593Smuzhiyun MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
54*4882a593Smuzhiyun MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
55*4882a593Smuzhiyun MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
56*4882a593Smuzhiyun MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
57*4882a593Smuzhiyun MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
58*4882a593Smuzhiyun MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
59*4882a593Smuzhiyun MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
60*4882a593Smuzhiyun MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
61*4882a593Smuzhiyun MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
62*4882a593Smuzhiyun MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
63*4882a593Smuzhiyun MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
64*4882a593Smuzhiyun MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
65*4882a593Smuzhiyun MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
66*4882a593Smuzhiyun MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
67*4882a593Smuzhiyun MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
68*4882a593Smuzhiyun MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
69*4882a593Smuzhiyun MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
72*4882a593Smuzhiyun MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
73*4882a593Smuzhiyun MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
74*4882a593Smuzhiyun MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
77*4882a593Smuzhiyun MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
78*4882a593Smuzhiyun MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
79*4882a593Smuzhiyun MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
80*4882a593Smuzhiyun MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
81*4882a593Smuzhiyun MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
82*4882a593Smuzhiyun MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
83*4882a593Smuzhiyun MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
84*4882a593Smuzhiyun MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
85*4882a593Smuzhiyun MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
86*4882a593Smuzhiyun MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
87*4882a593Smuzhiyun MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
88*4882a593Smuzhiyun MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
89*4882a593Smuzhiyun MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
90*4882a593Smuzhiyun MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
91*4882a593Smuzhiyun MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
94*4882a593Smuzhiyun MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
97*4882a593Smuzhiyun MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* -- Strick 5 -- */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* MMC0 */
102*4882a593Smuzhiyun MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
103*4882a593Smuzhiyun MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
104*4882a593Smuzhiyun MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
105*4882a593Smuzhiyun MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
106*4882a593Smuzhiyun MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
107*4882a593Smuzhiyun MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
108*4882a593Smuzhiyun (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
109*4882a593Smuzhiyun MX28_PAD_SSP0_SCK__SSP0_SCK |
110*4882a593Smuzhiyun (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* SPI2 (for flash) */
113*4882a593Smuzhiyun MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
114*4882a593Smuzhiyun MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
115*4882a593Smuzhiyun MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
116*4882a593Smuzhiyun MX28_PAD_SSP2_SS0__SSP2_D3 |
117*4882a593Smuzhiyun (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* -- Strick 6 -- */
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* I2C */
122*4882a593Smuzhiyun MX28_PAD_I2C0_SCL__I2C0_SCL,
123*4882a593Smuzhiyun MX28_PAD_I2C0_SDA__I2C0_SDA,
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* AUART0 */
126*4882a593Smuzhiyun MX28_PAD_AUART0_TX__AUART0_TX,
127*4882a593Smuzhiyun MX28_PAD_AUART0_RX__AUART0_RX,
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* MEGA interface */
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* Debug UART */
132*4882a593Smuzhiyun MX28_PAD_PWM0__DUART_RX,
133*4882a593Smuzhiyun MX28_PAD_PWM1__DUART_TX,
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* LED */
136*4882a593Smuzhiyun MX28_PAD_GPMI_D00__GPIO_0_0 | MUX_CONFIG_LED,
137*4882a593Smuzhiyun MX28_PAD_GPMI_D03__GPIO_0_3 | MUX_CONFIG_LED,
138*4882a593Smuzhiyun MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED,
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
board_init_ll(const uint32_t arg,const uint32_t * resptr)141*4882a593Smuzhiyun void board_init_ll(const uint32_t arg, const uint32_t *resptr)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
mxs_adjust_memory_params(uint32_t * dram_vals)146*4882a593Smuzhiyun void mxs_adjust_memory_params(uint32_t *dram_vals)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun dram_vals[0x74 >> 2] = 0x0f02010a;
149*4882a593Smuzhiyun }
150