1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/fsl_law.h> 12*4882a593Smuzhiyun #include <asm/mmu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * LAW(Local Access Window) configuration: 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * 0x0000_0000 0x0fff_ffff DDR 256M 18*4882a593Smuzhiyun * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M 19*4882a593Smuzhiyun * 0xa000_0000 0xbfff_ffff PCIe MEM 512M 20*4882a593Smuzhiyun * 0xe000_0000 0xe000_ffff CCSR 1M 21*4882a593Smuzhiyun * 0xe200_0000 0xe27f_ffff PCI1 IO 8M 22*4882a593Smuzhiyun * 0xe280_0000 0xe2ff_ffff PCIe IO 8M 23*4882a593Smuzhiyun * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M 24*4882a593Smuzhiyun * 0xf000_0000 0xf7ff_ffff SDRAM 128M 25*4882a593Smuzhiyun * 0xf8b0_0000 0xf80f_ffff EEPROM 1M 26*4882a593Smuzhiyun * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * If swapped CS0/CS6 via JP12+SW2.8: 29*4882a593Smuzhiyun * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M 30*4882a593Smuzhiyun * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * Notes: 33*4882a593Smuzhiyun * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. 34*4882a593Smuzhiyun * If flash is 8M at default position (last 8M), no LAW needed. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct law_entry law_table[] = { 38*4882a593Smuzhiyun #ifdef CONFIG_SYS_ALT_BOOT 39*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC), 40*4882a593Smuzhiyun #else 41*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC), 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun #ifndef CONFIG_SPD_EEPROM 44*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), 45*4882a593Smuzhiyun #endif 46*4882a593Smuzhiyun #ifdef CONFIG_SYS_LBC_SDRAM_BASE 47*4882a593Smuzhiyun /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ 48*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), 49*4882a593Smuzhiyun #else 50*4882a593Smuzhiyun /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */ 51*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun int num_law_entries = ARRAY_SIZE(law_table); 56