1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2008-2009 Samsung Electronics
3*4882a593Smuzhiyun * Kyungmin Park <kyungmin.park@samsung.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <linux/compat.h>
10*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
11*4882a593Smuzhiyun #include <linux/mtd/onenand.h>
12*4882a593Smuzhiyun #include <linux/mtd/samsung_onenand.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <onenand_uboot.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <asm/arch/clock.h>
18*4882a593Smuzhiyun
onenand_board_init(struct mtd_info * mtd)19*4882a593Smuzhiyun int onenand_board_init(struct mtd_info *mtd)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun struct onenand_chip *this = mtd->priv;
22*4882a593Smuzhiyun struct s5pc100_clock *clk =
23*4882a593Smuzhiyun (struct s5pc100_clock *)samsung_get_base_clock();
24*4882a593Smuzhiyun struct samsung_onenand *onenand;
25*4882a593Smuzhiyun int value;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun this->base = (void *)S5PC100_ONENAND_BASE;
28*4882a593Smuzhiyun onenand = (struct samsung_onenand *)this->base;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* D0 Domain memory clock gating */
31*4882a593Smuzhiyun value = readl(&clk->gate_d01);
32*4882a593Smuzhiyun value &= ~(1 << 2); /* CLK_ONENANDC */
33*4882a593Smuzhiyun value |= (1 << 2);
34*4882a593Smuzhiyun writel(value, &clk->gate_d01);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun value = readl(&clk->src0);
37*4882a593Smuzhiyun value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
38*4882a593Smuzhiyun value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
39*4882a593Smuzhiyun writel(value, &clk->src0);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun value = readl(&clk->div1);
42*4882a593Smuzhiyun value &= ~(3 << 16); /* PCLKD1_RATIO */
43*4882a593Smuzhiyun value |= (1 << 16);
44*4882a593Smuzhiyun writel(value, &clk->div1);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun while (!(readl(&onenand->int_err_stat) & RST_CMP))
49*4882a593Smuzhiyun continue;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun writel(RST_CMP, &onenand->int_err_ack);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * Access_Clock [2:0]
55*4882a593Smuzhiyun * 166 MHz, 134 Mhz : 3
56*4882a593Smuzhiyun * 100 Mhz, 60 Mhz : 2
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun writel(0x3, &onenand->acc_clock);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun writel(INT_ERR_ALL, &onenand->int_err_mask);
61*4882a593Smuzhiyun writel(1 << 0, &onenand->int_pin_en); /* Enable */
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun value = readl(&onenand->int_err_mask);
64*4882a593Smuzhiyun value &= ~RDY_ACT;
65*4882a593Smuzhiyun writel(value, &onenand->int_err_mask);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun s3c_onenand_init(mtd);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
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