1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013 Samsung Electronics
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <usb.h>
9*4882a593Smuzhiyun #include <asm/gpio.h>
10*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
11*4882a593Smuzhiyun #include <asm/arch/dwmmc.h>
12*4882a593Smuzhiyun #include <asm/arch/power.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #ifdef CONFIG_USB_EHCI_EXYNOS
board_usb_init(int index,enum usb_init_type init)17*4882a593Smuzhiyun int board_usb_init(int index, enum usb_init_type init)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun /* Configure gpios for usb 3503 hub:
20*4882a593Smuzhiyun * disconnect, toggle reset and connect
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun gpio_request(EXYNOS5_GPIO_D17, "usb_connect");
23*4882a593Smuzhiyun gpio_request(EXYNOS5_GPIO_X35, "usb_reset");
24*4882a593Smuzhiyun gpio_direction_output(EXYNOS5_GPIO_D17, 0);
25*4882a593Smuzhiyun gpio_direction_output(EXYNOS5_GPIO_X35, 0);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun gpio_direction_output(EXYNOS5_GPIO_X35, 1);
28*4882a593Smuzhiyun gpio_direction_output(EXYNOS5_GPIO_D17, 1);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun
board_init(void)34*4882a593Smuzhiyun int board_init(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
dram_init(void)40*4882a593Smuzhiyun int dram_init(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun int i;
43*4882a593Smuzhiyun u32 addr;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
46*4882a593Smuzhiyun addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
47*4882a593Smuzhiyun gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
power_init_board(void)52*4882a593Smuzhiyun int power_init_board(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun set_ps_hold_ctrl();
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
dram_init_banksize(void)58*4882a593Smuzhiyun int dram_init_banksize(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun int i;
61*4882a593Smuzhiyun u32 addr, size;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
64*4882a593Smuzhiyun addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
65*4882a593Smuzhiyun size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun gd->bd->bi_dram[i].start = addr;
68*4882a593Smuzhiyun gd->bd->bi_dram[i].size = size;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #ifdef CONFIG_MMC
board_mmc_init(bd_t * bis)75*4882a593Smuzhiyun int board_mmc_init(bd_t *bis)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int ret;
78*4882a593Smuzhiyun /* dwmmc initializattion for available channels */
79*4882a593Smuzhiyun ret = exynos_dwmmc_init(gd->fdt_blob);
80*4882a593Smuzhiyun if (ret)
81*4882a593Smuzhiyun debug("dwmmc init failed\n");
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return ret;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun #endif
86*4882a593Smuzhiyun
board_uart_init(void)87*4882a593Smuzhiyun static int board_uart_init(void)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun int err = 0, uart_id;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
92*4882a593Smuzhiyun err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
93*4882a593Smuzhiyun if (err) {
94*4882a593Smuzhiyun debug("UART%d not configured\n",
95*4882a593Smuzhiyun (uart_id - PERIPH_ID_UART0));
96*4882a593Smuzhiyun return err;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun return err;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)103*4882a593Smuzhiyun int board_early_init_f(void)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun int err;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun err = board_uart_init();
108*4882a593Smuzhiyun if (err) {
109*4882a593Smuzhiyun debug("UART init failed\n");
110*4882a593Smuzhiyun return err;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun return err;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun #endif
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)117*4882a593Smuzhiyun int checkboard(void)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun printf("\nBoard: Arndale\n");
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun #endif
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #ifdef CONFIG_S5P_PA_SYSRAM
smp_set_core_boot_addr(unsigned long addr,int corenr)126*4882a593Smuzhiyun void smp_set_core_boot_addr(unsigned long addr, int corenr)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun writel(addr, CONFIG_S5P_PA_SYSRAM);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* make sure this write is really executed */
131*4882a593Smuzhiyun __asm__ volatile ("dsb\n");
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun #endif
134