1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Stout board CPLD definition 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Europe GmbH 5*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * Copyright (C) 2015 Cogent Embedded, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _CPLD_H_ 12*4882a593Smuzhiyun #define _CPLD_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* power-up behaviour */ 15*4882a593Smuzhiyun #define MODE_MSK_FREE_RUN 0x00000001 16*4882a593Smuzhiyun #define MODE_VAL_FREE_RUN 0x00000000 17*4882a593Smuzhiyun #define MODE_MSK_STEP_UP 0x00000001 18*4882a593Smuzhiyun #define MODE_VAL_STEP_UP 0x00000000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* boot source */ 21*4882a593Smuzhiyun #define MODE_MSK_BOOT_SQPI_16KB_FAST 0x0000000E 22*4882a593Smuzhiyun #define MODE_VAL_BOOT_SQPI_16KB_FAST 0x00000004 23*4882a593Smuzhiyun #define MODE_MSK_BOOT_SQPI_16KB_SLOW 0x0000000E 24*4882a593Smuzhiyun #define MODE_VAL_BOOT_SQPI_16KB_SLOW 0x00000008 25*4882a593Smuzhiyun #define MODE_MSK_BOOT_SQPI_4KB_SLOW 0x0000000E 26*4882a593Smuzhiyun #define MODE_VAL_BOOT_SQPI_4KB_SLOW 0x0000000C 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* booting CPU */ 29*4882a593Smuzhiyun #define MODE_MSK_BOOT_CA15 0x000000C0 30*4882a593Smuzhiyun #define MODE_VAL_BOOT_CA15 0x00000000 31*4882a593Smuzhiyun #define MODE_MSK_BOOT_CA7 0x000000C0 32*4882a593Smuzhiyun #define MODE_VAL_BOOT_CA7 0x00000040 33*4882a593Smuzhiyun #define MODE_MSK_BOOT_SH4 0x000000C0 34*4882a593Smuzhiyun #define MODE_VAL_BOOT_SH4 0x000000C0 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* JTAG connection */ 37*4882a593Smuzhiyun #define MODE_MSK_JTAG_CORESIGHT 0xC0301C00 38*4882a593Smuzhiyun #define MODE_VAL_JTAG_CORESIGHT 0x00200000 39*4882a593Smuzhiyun #define MODE_MSK_JTAG_SH4 0xC0301C00 40*4882a593Smuzhiyun #define MODE_VAL_JTAG_SH4 0x00300000 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* DDR3 (PLL) speed */ 43*4882a593Smuzhiyun #define MODE_MSK_DDR3_1600 0x00080000 44*4882a593Smuzhiyun #define MODE_VAL_DDR3_1600 0x00000000 45*4882a593Smuzhiyun #define MODE_MSK_DDR3_1333 0x00080000 46*4882a593Smuzhiyun #define MODE_VAL_DDR3_1333 0x00080000 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* ComboPhy0 mode */ 49*4882a593Smuzhiyun #define MODE_MSK_PHY0_SATA0 0x01000000 50*4882a593Smuzhiyun #define MODE_VAL_PHY0_SATA0 0x00000000 51*4882a593Smuzhiyun #define MODE_MSK_PHY0_PCIE 0x01000000 52*4882a593Smuzhiyun #define MODE_VAL_PHY0_PCIE 0x01000000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* ComboPhy1 mode */ 55*4882a593Smuzhiyun #define MODE_MSK_PHY1_SATA1 0x00800000 56*4882a593Smuzhiyun #define MODE_VAL_PHY1_SATA1 0x00000000 57*4882a593Smuzhiyun #define MODE_MSK_PHY1_USB3 0x00800000 58*4882a593Smuzhiyun #define MODE_VAL_PHY1_USB3 0x00800000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * Illegal multiplexer combinations. 62*4882a593Smuzhiyun * MUX Conflicts 63*4882a593Smuzhiyun * name with any one of 64*4882a593Smuzhiyun * VIN0_BT656 VIN0_full, SD2 65*4882a593Smuzhiyun * VIN0_full VIN0_BT656, SD2, AVB, VIN2_(all) 66*4882a593Smuzhiyun * VIN1_BT656 VIN1_(others), SD0 67*4882a593Smuzhiyun * VIN1_10bit VIN1_(others), SD0, VIN3_with*, I2C1 68*4882a593Smuzhiyun * VIN1_12bit VIN1_(others), SD0, VIN3_with*, I2C1, SCIFA0_(all) 69*4882a593Smuzhiyun * VIN2_BT656 VIN0_full, VIN2_(others), AVB, 70*4882a593Smuzhiyun * VIN2_withSYNC VIN0_full, VIN2_(others), AVB, I2C1, SCIFA0_(all), 71*4882a593Smuzhiyun * VIN3_with* 72*4882a593Smuzhiyun * VIN2_withFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all) 73*4882a593Smuzhiyun * VIN2_withSYNCandFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all), I2C1, 74*4882a593Smuzhiyun * SCIFA0_(all), VIN3_with* 75*4882a593Smuzhiyun * VIN3_BT656 VIN3_(others), IRQ3 76*4882a593Smuzhiyun * VIN3_withFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC, 77*4882a593Smuzhiyun * VIN2_withSYNCandFIELD, VIN1_10bit 78*4882a593Smuzhiyun * VIN3_withSYNCandFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC, 79*4882a593Smuzhiyun * VIN2_withSYNCandFIELD, VIN1_10bit, I2C1 80*4882a593Smuzhiyun * AVB VIN0_full, VIN2_(all) 81*4882a593Smuzhiyun * QSPI_ONBOARD VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_COMEXPRESS 82*4882a593Smuzhiyun * QSPI_COMEXPRESS VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_ONBOARD 83*4882a593Smuzhiyun * I2C1 VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, 84*4882a593Smuzhiyun * VIN3_withSYNCandFIELD 85*4882a593Smuzhiyun * IRQ3 VIN3_(all) 86*4882a593Smuzhiyun * SCIFA0_USB VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, 87*4882a593Smuzhiyun * SCIFA0_COMEXPRESS 88*4882a593Smuzhiyun * SCIFA0_COMEXPRESS VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, 89*4882a593Smuzhiyun * SCIFA0_USB 90*4882a593Smuzhiyun * SCIFA2 PWM210 91*4882a593Smuzhiyun * ETH_ONBOARD ETH_COMEXPRESS 92*4882a593Smuzhiyun * ETH_COMEXPRESS ETH_ONBOARD 93*4882a593Smuzhiyun * SD0 VIN1_(all) 94*4882a593Smuzhiyun * SD2 VIN0_(all) 95*4882a593Smuzhiyun * PWM210 SCIFA2 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* connected to COM Express connector and CN6 for camera, BT656 only */ 99*4882a593Smuzhiyun #define MUX_MSK_VIN0_BT656 0x00001001 100*4882a593Smuzhiyun #define MUX_VAL_VIN0_BT656 0x00000000 101*4882a593Smuzhiyun /* connected to COM Express connector and CN6 for camera, all modes */ 102*4882a593Smuzhiyun #define MUX_MSK_VIN0_full 0x00001007 103*4882a593Smuzhiyun #define MUX_VAL_VIN0_full 0x00000002 104*4882a593Smuzhiyun /* connected to COM Express connector, BT656 only */ 105*4882a593Smuzhiyun #define MUX_MSK_VIN1_BT656 0x00000801 106*4882a593Smuzhiyun #define MUX_VAL_VIN1_BT656 0x00000800 107*4882a593Smuzhiyun /* connected to COM Express connector, all 10-bit modes */ 108*4882a593Smuzhiyun #define MUX_MSK_VIN1_10bit 0x00000821 109*4882a593Smuzhiyun #define MUX_VAL_VIN1_10bit 0x00000800 110*4882a593Smuzhiyun /* connected to COM Express connector, all 12-bit modes */ 111*4882a593Smuzhiyun #define MUX_MSK_VIN1_12bit 0x000008A1 112*4882a593Smuzhiyun #define MUX_VAL_VIN1_12bit 0x00000880 113*4882a593Smuzhiyun /* connected to COM Express connector, BT656 only */ 114*4882a593Smuzhiyun #define MUX_MSK_VIN2_BT656 0x00000007 115*4882a593Smuzhiyun #define MUX_VAL_VIN2_BT656 0x00000006 116*4882a593Smuzhiyun /* connected to COM Express connector, modes with sync signals */ 117*4882a593Smuzhiyun #define MUX_MSK_VIN2_withSYNC 0x000000A7 118*4882a593Smuzhiyun #define MUX_VAL_VIN2_withSYNC 0x00000086 119*4882a593Smuzhiyun /* connected to COM Express connector, modes with field, clken signals */ 120*4882a593Smuzhiyun #define MUX_MSK_VIN2_withFIELD 0x0000000F 121*4882a593Smuzhiyun #define MUX_VAL_VIN2_withFIELD 0x0000000E 122*4882a593Smuzhiyun /* connected to COM Express connector, modes with sync, field, clken signals */ 123*4882a593Smuzhiyun #define MUX_MSK_VIN2_withSYNCandFIELD 0x000000AF 124*4882a593Smuzhiyun #define MUX_VAL_VIN2_withSYNCandFIELD 0x0000008E 125*4882a593Smuzhiyun /* connected to COM Express connector, BT656 only */ 126*4882a593Smuzhiyun #define MUX_MSK_VIN3_BT656 0x00000101 127*4882a593Smuzhiyun #define MUX_VAL_VIN3_BT656 0x00000100 128*4882a593Smuzhiyun /* connected to COM Express connector, modes with field, clken signals */ 129*4882a593Smuzhiyun #define MUX_MSK_VIN3_withFIELD 0x00000121 130*4882a593Smuzhiyun #define MUX_VAL_VIN3_withFIELD 0x00000120 131*4882a593Smuzhiyun /* connected to COM Express connector, modes with sync, field, clken signals */ 132*4882a593Smuzhiyun #define MUX_MSK_VIN3_withSYNCandFIELD 0x00000161 133*4882a593Smuzhiyun #define MUX_VAL_VIN3_withSYNCandFIELD 0x00000120 134*4882a593Smuzhiyun /* connected to COM Express connector (RGMII) */ 135*4882a593Smuzhiyun #define MUX_MSK_AVB 0x00000003 136*4882a593Smuzhiyun #define MUX_VAL_AVB 0x00000000 137*4882a593Smuzhiyun /* connected to on-board QSPI flash */ 138*4882a593Smuzhiyun #define MUX_MSK_QSPI_ONBOARD 0x00000019 139*4882a593Smuzhiyun #define MUX_VAL_QSPI_ONBOARD 0x00000000 140*4882a593Smuzhiyun /* connected to COM Express connector */ 141*4882a593Smuzhiyun #define MUX_MSK_QSPI_COMEXPRESS 0x00000019 142*4882a593Smuzhiyun #define MUX_VAL_QSPI_COMEXPRESS 0x00000010 143*4882a593Smuzhiyun /* connected to COM Express connector and PMIC */ 144*4882a593Smuzhiyun #define MUX_MSK_I2C1 0x00000061 145*4882a593Smuzhiyun #define MUX_VAL_I2C1 0x00000060 146*4882a593Smuzhiyun /* connected to HDMI driver */ 147*4882a593Smuzhiyun #define MUX_MSK_IRQ3 0x00000101 148*4882a593Smuzhiyun #define MUX_VAL_IRQ3 0x00000000 149*4882a593Smuzhiyun /* connected to USB/FTDI */ 150*4882a593Smuzhiyun #define MUX_MSK_SCIFA0_USB 0x00004081 151*4882a593Smuzhiyun #define MUX_VAL_SCIFA0_USB 0x00004000 152*4882a593Smuzhiyun /* connected to COM Express connector */ 153*4882a593Smuzhiyun #define MUX_MSK_SCIFA0_COMEXPRESS 0x00004081 154*4882a593Smuzhiyun #define MUX_VAL_SCIFA0_COMEXPRESS 0x00000000 155*4882a593Smuzhiyun /* connected to COM Express connector */ 156*4882a593Smuzhiyun #define MUX_MSK_SCIFA2 0x00002001 157*4882a593Smuzhiyun #define MUX_VAL_SCIFA2 0x00000000 158*4882a593Smuzhiyun /* connected to on-board 10/100 Phy */ 159*4882a593Smuzhiyun #define MUX_MSK_ETH_ONBOARD 0x00000600 160*4882a593Smuzhiyun #define MUX_VAL_ETH_ONBOARD 0x00000000 161*4882a593Smuzhiyun /* connected to COM Express connector (RMII) */ 162*4882a593Smuzhiyun #define MUX_MSK_ETH_COMEXPRESS 0x00000600 163*4882a593Smuzhiyun #define MUX_VAL_ETH_COMEXPRESS 0x00000400 164*4882a593Smuzhiyun /* connected to on-board MicroSD slot */ 165*4882a593Smuzhiyun #define MUX_MSK_SD0 0x00000801 166*4882a593Smuzhiyun #define MUX_VAL_SD0 0x00000000 167*4882a593Smuzhiyun /* connected to COM Express connector */ 168*4882a593Smuzhiyun #define MUX_MSK_SD2 0x00001001 169*4882a593Smuzhiyun #define MUX_VAL_SD2 0x00001000 170*4882a593Smuzhiyun /* connected to COM Express connector */ 171*4882a593Smuzhiyun #define MUX_MSK_PWM210 0x00002001 172*4882a593Smuzhiyun #define MUX_VAL_PWM210 0x00002000 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define HDMI_MSK 0x07 175*4882a593Smuzhiyun #define HDMI_OFF 0x00 176*4882a593Smuzhiyun #define HDMI_ONBOARD 0x07 177*4882a593Smuzhiyun #define HDMI_COMEXPRESS 0x05 178*4882a593Smuzhiyun #define HDMI_ONBOARD_NODDC 0x03 179*4882a593Smuzhiyun #define HDMI_COMEXPRESS_NODDC 0x01 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun void cpld_init(void); 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #endif /* _CPLD_H_ */ 184