1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/processor.h>
10*4882a593Smuzhiyun #include <asm/pci.h>
11*4882a593Smuzhiyun #include <netdev.h>
12*4882a593Smuzhiyun
checkboard(void)13*4882a593Smuzhiyun int checkboard(void)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
16*4882a593Smuzhiyun return 0;
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun
board_init(void)19*4882a593Smuzhiyun int board_init(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun return 0;
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static struct pci_controller hose;
pci_init_board(void)25*4882a593Smuzhiyun void pci_init_board(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun pci_sh7780_init(&hose);
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
board_eth_init(bd_t * bis)30*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun return pci_eth_init(bis);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #if defined(CONFIG_SH_32BIT)
do_pmb(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])36*4882a593Smuzhiyun int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun /* clear ITLB */
39*4882a593Smuzhiyun writel(0x00000004, 0xff000010);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* delete PMB for peripheral */
42*4882a593Smuzhiyun writel(0, PMB_ADDR_BASE(0));
43*4882a593Smuzhiyun writel(0, PMB_DATA_BASE(0));
44*4882a593Smuzhiyun writel(0, PMB_ADDR_BASE(1));
45*4882a593Smuzhiyun writel(0, PMB_DATA_BASE(1));
46*4882a593Smuzhiyun writel(0, PMB_ADDR_BASE(2));
47*4882a593Smuzhiyun writel(0, PMB_DATA_BASE(2));
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
50*4882a593Smuzhiyun writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
51*4882a593Smuzhiyun writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
52*4882a593Smuzhiyun writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
53*4882a593Smuzhiyun writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun U_BOOT_CMD(
59*4882a593Smuzhiyun pmb, 1, 1, do_pmb,
60*4882a593Smuzhiyun "pmb - PMB setting\n",
61*4882a593Smuzhiyun "\n"
62*4882a593Smuzhiyun " - PMB setting for all SDRAM mapping"
63*4882a593Smuzhiyun );
64*4882a593Smuzhiyun #endif
65