1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2008 Renesas Solutions Corp. 3*4882a593Smuzhiyun * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 4*4882a593Smuzhiyun * Copyright (C) 2007 Kenati Technologies, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * board/sh7763rdp/lowlevel_init.S 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include <config.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <asm/processor.h> 14*4882a593Smuzhiyun#include <asm/macro.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun .global lowlevel_init 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun .text 19*4882a593Smuzhiyun .align 2 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunlowlevel_init: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun write32 WDTBST_A, WDTBST_D /* 28*4882a593Smuzhiyun * 0xFFCC0008 29*4882a593Smuzhiyun * Watchdog Base Stop Time Register 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */ 33*4882a593Smuzhiyun /* Instruction Cache Invalidate */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */ 36*4882a593Smuzhiyun /* TI == TLB Invalidate bit */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun write32 RAMCR_A, RAMCR_D 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun mov.l MMSELR_A, r1 45*4882a593Smuzhiyun mov.l MMSELR_D, r0 46*4882a593Smuzhiyun synco 47*4882a593Smuzhiyun mov.l r0, @r1 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun mov.l @r1, r2 /* execute two reads after setting MMSELR */ 50*4882a593Smuzhiyun mov.l @r1, r2 51*4882a593Smuzhiyun synco 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* issue memory read */ 54*4882a593Smuzhiyun mov.l DDRSD_START_A, r1 /* memory address to read*/ 55*4882a593Smuzhiyun mov.l @r1, r0 56*4882a593Smuzhiyun synco 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun write32 MIM8_A, MIM8_D 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun write32 MIMC_A, MIMC_D1 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun write32 STRC_A, STRC_D 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun write32 SDR4_A, SDR4_D 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun write32 MIMC_A, MIMC_D2 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun nop 69*4882a593Smuzhiyun nop 70*4882a593Smuzhiyun nop 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun write32 SCR4_A, SCR4_D3 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun write32 SCR4_A, SCR4_D2 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun write32 SDMR02000_A, SDMR02000_D 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun write32 SDMR00B08_A, SDMR00B08_D 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun write32 SCR4_A, SCR4_D2 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun write32 SCR4_A, SCR4_D4 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun nop 85*4882a593Smuzhiyun nop 86*4882a593Smuzhiyun nop 87*4882a593Smuzhiyun nop 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun write32 SCR4_A, SCR4_D4 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun nop 92*4882a593Smuzhiyun nop 93*4882a593Smuzhiyun nop 94*4882a593Smuzhiyun nop 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun write32 SDMR00308_A, SDMR00308_D 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun write32 MIMC_A, MIMC_D3 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun mov.l SCR4_A, r1 101*4882a593Smuzhiyun mov.l SCR4_D1, r0 102*4882a593Smuzhiyun mov.l DELAY60_D, r3 103*4882a593Smuzhiyun 104*4882a593Smuzhiyundelay_loop_60: 105*4882a593Smuzhiyun mov.l r0, @r1 106*4882a593Smuzhiyun dt r3 107*4882a593Smuzhiyun bf delay_loop_60 108*4882a593Smuzhiyun nop 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyunbsc_init: 113*4882a593Smuzhiyun write32 BCR_A, BCR_D 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun write32 CS0BCR_A, CS0BCR_D 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun write32 CS1BCR_A, CS1BCR_D 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun write32 CS2BCR_A, CS2BCR_D 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun write32 CS4BCR_A, CS4BCR_D 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun write32 CS5BCR_A, CS5BCR_D 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun write32 CS6BCR_A, CS6BCR_D 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun write32 CS0WCR_A, CS0WCR_D 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun write32 CS1WCR_A, CS1WCR_D 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun write32 CS2WCR_A, CS2WCR_D 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun write32 CS4WCR_A, CS4WCR_D 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun write32 CS5WCR_A, CS5WCR_D 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun write32 CS6WCR_A, CS6WCR_D 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun write32 CS5PCR_A, CS5PCR_D 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun write32 CS6PCR_A, CS6PCR_D 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun mov.l DELAY200_D, r3 144*4882a593Smuzhiyun 145*4882a593Smuzhiyundelay_loop_200: 146*4882a593Smuzhiyun dt r3 147*4882a593Smuzhiyun bf delay_loop_200 148*4882a593Smuzhiyun nop 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun write16 PSEL0_A, PSEL0_D 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun write16 PSEL1_A, PSEL1_D 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun write32 ICR0_A, ICR0_D 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun stc sr, r0 /* BL bit off(init=ON) */ 157*4882a593Smuzhiyun mov.l SR_MASK_D, r1 158*4882a593Smuzhiyun and r1, r0 159*4882a593Smuzhiyun ldc r0, sr 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun rts 162*4882a593Smuzhiyun nop 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun .align 2 165*4882a593Smuzhiyun 166*4882a593SmuzhiyunDELAY60_D: .long 60 167*4882a593SmuzhiyunDELAY200_D: .long 17800 168*4882a593Smuzhiyun 169*4882a593SmuzhiyunCCR_A: .long 0xFF00001C 170*4882a593SmuzhiyunMMUCR_A: .long 0xFF000010 171*4882a593SmuzhiyunRAMCR_A: .long 0xFF000074 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun/* Low power mode control */ 174*4882a593SmuzhiyunMSTPCR0_A: .long 0xFFC80030 175*4882a593SmuzhiyunMSTPCR1_A: .long 0xFFC80038 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun/* RWBT */ 178*4882a593SmuzhiyunWDTST_A: .long 0xFFCC0000 179*4882a593SmuzhiyunWDTCSR_A: .long 0xFFCC0004 180*4882a593SmuzhiyunWDTBST_A: .long 0xFFCC0008 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun/* BSC */ 183*4882a593SmuzhiyunMMSELR_A: .long 0xFE600020 184*4882a593SmuzhiyunBCR_A: .long 0xFF801000 185*4882a593SmuzhiyunCS0BCR_A: .long 0xFF802000 186*4882a593SmuzhiyunCS1BCR_A: .long 0xFF802010 187*4882a593SmuzhiyunCS2BCR_A: .long 0xFF802020 188*4882a593SmuzhiyunCS4BCR_A: .long 0xFF802040 189*4882a593SmuzhiyunCS5BCR_A: .long 0xFF802050 190*4882a593SmuzhiyunCS6BCR_A: .long 0xFF802060 191*4882a593SmuzhiyunCS0WCR_A: .long 0xFF802008 192*4882a593SmuzhiyunCS1WCR_A: .long 0xFF802018 193*4882a593SmuzhiyunCS2WCR_A: .long 0xFF802028 194*4882a593SmuzhiyunCS4WCR_A: .long 0xFF802048 195*4882a593SmuzhiyunCS5WCR_A: .long 0xFF802058 196*4882a593SmuzhiyunCS6WCR_A: .long 0xFF802068 197*4882a593SmuzhiyunCS5PCR_A: .long 0xFF802070 198*4882a593SmuzhiyunCS6PCR_A: .long 0xFF802080 199*4882a593SmuzhiyunDDRSD_START_A: .long 0xAC000000 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun/* INTC */ 202*4882a593SmuzhiyunICR0_A: .long 0xFFD00000 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun/* DDR I/F */ 205*4882a593SmuzhiyunMIM8_A: .long 0xFE800008 206*4882a593SmuzhiyunMIMC_A: .long 0xFE80000C 207*4882a593SmuzhiyunSCR4_A: .long 0xFE800014 208*4882a593SmuzhiyunSTRC_A: .long 0xFE80001C 209*4882a593SmuzhiyunSDR4_A: .long 0xFE800034 210*4882a593SmuzhiyunSDMR00308_A: .long 0xFE900308 211*4882a593SmuzhiyunSDMR00B08_A: .long 0xFE900B08 212*4882a593SmuzhiyunSDMR02000_A: .long 0xFE902000 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun/* GPIO */ 215*4882a593SmuzhiyunPSEL0_A: .long 0xFFEF0070 216*4882a593SmuzhiyunPSEL1_A: .long 0xFFEF0072 217*4882a593Smuzhiyun 218*4882a593SmuzhiyunCCR_CACHE_ICI_D:.long 0x00000800 219*4882a593SmuzhiyunCCR_CACHE_D_2: .long 0x00000103 220*4882a593SmuzhiyunMMU_CONTROL_TI_D:.long 0x00000004 221*4882a593SmuzhiyunRAMCR_D: .long 0x00000200 222*4882a593SmuzhiyunMSTPCR0_D: .long 0x00000000 223*4882a593SmuzhiyunMSTPCR1_D: .long 0x00000000 224*4882a593Smuzhiyun 225*4882a593SmuzhiyunMMSELR_D: .long 0xa5a50000 226*4882a593SmuzhiyunBCR_D: .long 0x00000000 227*4882a593SmuzhiyunCS0BCR_D: .long 0x77777770 228*4882a593SmuzhiyunCS1BCR_D: .long 0x77777670 229*4882a593SmuzhiyunCS2BCR_D: .long 0x77777670 230*4882a593SmuzhiyunCS4BCR_D: .long 0x77777670 231*4882a593SmuzhiyunCS5BCR_D: .long 0x77777670 232*4882a593SmuzhiyunCS6BCR_D: .long 0x77777670 233*4882a593SmuzhiyunCS0WCR_D: .long 0x7777770F 234*4882a593SmuzhiyunCS1WCR_D: .long 0x22000002 235*4882a593SmuzhiyunCS2WCR_D: .long 0x7777770F 236*4882a593SmuzhiyunCS4WCR_D: .long 0x7777770F 237*4882a593SmuzhiyunCS5WCR_D: .long 0x7777770F 238*4882a593SmuzhiyunCS6WCR_D: .long 0x7777770F 239*4882a593SmuzhiyunCS5PCR_D: .long 0x77000000 240*4882a593SmuzhiyunCS6PCR_D: .long 0x77000000 241*4882a593SmuzhiyunICR0_D: .long 0x00E00000 242*4882a593SmuzhiyunMIM8_D: .long 0x00000000 243*4882a593SmuzhiyunMIMC_D1: .long 0x01d10008 244*4882a593SmuzhiyunMIMC_D2: .long 0x01d10009 245*4882a593SmuzhiyunMIMC_D3: .long 0x01d10209 246*4882a593SmuzhiyunSCR4_D1: .long 0x00000001 247*4882a593SmuzhiyunSCR4_D2: .long 0x00000002 248*4882a593SmuzhiyunSCR4_D3: .long 0x00000003 249*4882a593SmuzhiyunSCR4_D4: .long 0x00000004 250*4882a593SmuzhiyunSTRC_D: .long 0x000f3980 251*4882a593SmuzhiyunSDR4_D: .long 0x00000300 252*4882a593SmuzhiyunSDMR00308_D: .long 0x00000000 253*4882a593SmuzhiyunSDMR00B08_D: .long 0x00000000 254*4882a593SmuzhiyunSDMR02000_D: .long 0x00000000 255*4882a593SmuzhiyunPSEL0_D: .word 0x00000001 256*4882a593SmuzhiyunPSEL1_D: .word 0x00000244 257*4882a593SmuzhiyunSR_MASK_D: .long 0xEFFFFF0F 258*4882a593SmuzhiyunWDTST_D: .long 0x5A000FFF 259*4882a593SmuzhiyunWDTCSR_D: .long 0xA5000000 260*4882a593SmuzhiyunWDTBST_D: .long 0x55000000 261