1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2011 Renesas Solutions Corp.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU Lesser
5*4882a593Smuzhiyun * General Public License. See the file "COPYING.LIB" in the main
6*4882a593Smuzhiyun * directory of this archive for more details.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define CONFIG_RAM_BOOT_PHYS 0x4ef80000
12*4882a593Smuzhiyun #if defined(CONFIG_SH7757_OFFSET_SPI)
13*4882a593Smuzhiyun #define CONFIG_SPI_ADDR 0x00010000
14*4882a593Smuzhiyun #else
15*4882a593Smuzhiyun #define CONFIG_SPI_ADDR 0x00000000
16*4882a593Smuzhiyun #endif
17*4882a593Smuzhiyun #define CONFIG_SPI_LENGTH 0x00030000
18*4882a593Smuzhiyun #define CONFIG_RAM_BOOT 0x8ef80000
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define SPIWDMADR 0xFE001018
21*4882a593Smuzhiyun #define SPIWDMCNTR 0xFE001020
22*4882a593Smuzhiyun #define SPIDMCOR 0xFE001028
23*4882a593Smuzhiyun #define SPIDMINTSR 0xFE001188
24*4882a593Smuzhiyun #define SPIDMINTMR 0xFE001190
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define SPIDMINTSR_DMEND 0x00000004
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define TBR 0xFE002000
29*4882a593Smuzhiyun #define RBR 0xFE002000
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define CR1 0xFE002008
32*4882a593Smuzhiyun #define CR2 0xFE002010
33*4882a593Smuzhiyun #define CR3 0xFE002018
34*4882a593Smuzhiyun #define CR4 0xFE002020
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* CR1 */
37*4882a593Smuzhiyun #define SPI_TBE 0x80
38*4882a593Smuzhiyun #define SPI_TBF 0x40
39*4882a593Smuzhiyun #define SPI_RBE 0x20
40*4882a593Smuzhiyun #define SPI_RBF 0x10
41*4882a593Smuzhiyun #define SPI_PFONRD 0x08
42*4882a593Smuzhiyun #define SPI_SSDB 0x04
43*4882a593Smuzhiyun #define SPI_SSD 0x02
44*4882a593Smuzhiyun #define SPI_SSA 0x01
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* CR2 */
47*4882a593Smuzhiyun #define SPI_RSTF 0x80
48*4882a593Smuzhiyun #define SPI_LOOPBK 0x40
49*4882a593Smuzhiyun #define SPI_CPOL 0x20
50*4882a593Smuzhiyun #define SPI_CPHA 0x10
51*4882a593Smuzhiyun #define SPI_L1M0 0x08
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* CR4 */
54*4882a593Smuzhiyun #define SPI_TBEI 0x80
55*4882a593Smuzhiyun #define SPI_TBFI 0x40
56*4882a593Smuzhiyun #define SPI_RBEI 0x20
57*4882a593Smuzhiyun #define SPI_RBFI 0x10
58*4882a593Smuzhiyun #define SPI_SSS 0x01
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
61*4882a593Smuzhiyun #define spi_read(addr) (*(volatile unsigned long *)(addr))
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* M25P80 */
64*4882a593Smuzhiyun #define M25_READ 0x03
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
spi_reset(void)67*4882a593Smuzhiyun static void __uses_spiboot2 spi_reset(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun spi_write(0xfe, CR1);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun spi_write(0, SPIDMCOR);
72*4882a593Smuzhiyun spi_write(0x00, CR1);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
75*4882a593Smuzhiyun spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
spi_read_flash(void * buf,unsigned long addr,unsigned long len)78*4882a593Smuzhiyun static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
79*4882a593Smuzhiyun unsigned long len)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun spi_write(M25_READ, TBR);
82*4882a593Smuzhiyun spi_write((addr >> 16) & 0xFF, TBR);
83*4882a593Smuzhiyun spi_write((addr >> 8) & 0xFF, TBR);
84*4882a593Smuzhiyun spi_write(addr & 0xFF, TBR);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
87*4882a593Smuzhiyun spi_write((unsigned long)buf, SPIWDMADR);
88*4882a593Smuzhiyun spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
89*4882a593Smuzhiyun spi_write(1, SPIDMCOR);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun spi_write(0xff, CR3);
92*4882a593Smuzhiyun spi_write(spi_read(CR1) | SPI_SSDB, CR1);
93*4882a593Smuzhiyun spi_write(spi_read(CR1) | SPI_SSA, CR1);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
96*4882a593Smuzhiyun ;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
spiboot_main(void)99*4882a593Smuzhiyun void __uses_spiboot2 spiboot_main(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun spi_reset();
104*4882a593Smuzhiyun spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
105*4882a593Smuzhiyun CONFIG_SPI_LENGTH);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun _start();
108*4882a593Smuzhiyun }
109