1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013 Renesas Solutions Corp.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #define CONFIG_SPI_ADDR 0x00000000
10*4882a593Smuzhiyun #define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000)
11*4882a593Smuzhiyun #define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE)
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SPIWDMADR 0xFE001018
14*4882a593Smuzhiyun #define SPIWDMCNTR 0xFE001020
15*4882a593Smuzhiyun #define SPIDMCOR 0xFE001028
16*4882a593Smuzhiyun #define SPIDMINTSR 0xFE001188
17*4882a593Smuzhiyun #define SPIDMINTMR 0xFE001190
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define SPIDMINTSR_DMEND 0x00000004
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define TBR 0xFE002000
22*4882a593Smuzhiyun #define RBR 0xFE002000
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define CR1 0xFE002008
25*4882a593Smuzhiyun #define CR2 0xFE002010
26*4882a593Smuzhiyun #define CR3 0xFE002018
27*4882a593Smuzhiyun #define CR4 0xFE002020
28*4882a593Smuzhiyun #define CR7 0xFE002038
29*4882a593Smuzhiyun #define CR8 0xFE002040
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* CR1 */
32*4882a593Smuzhiyun #define SPI_TBE 0x80
33*4882a593Smuzhiyun #define SPI_TBF 0x40
34*4882a593Smuzhiyun #define SPI_RBE 0x20
35*4882a593Smuzhiyun #define SPI_RBF 0x10
36*4882a593Smuzhiyun #define SPI_PFONRD 0x08
37*4882a593Smuzhiyun #define SPI_SSDB 0x04
38*4882a593Smuzhiyun #define SPI_SSD 0x02
39*4882a593Smuzhiyun #define SPI_SSA 0x01
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* CR2 */
42*4882a593Smuzhiyun #define SPI_RSTF 0x80
43*4882a593Smuzhiyun #define SPI_LOOPBK 0x40
44*4882a593Smuzhiyun #define SPI_CPOL 0x20
45*4882a593Smuzhiyun #define SPI_CPHA 0x10
46*4882a593Smuzhiyun #define SPI_L1M0 0x08
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* CR4 */
49*4882a593Smuzhiyun #define SPI_TBEI 0x80
50*4882a593Smuzhiyun #define SPI_TBFI 0x40
51*4882a593Smuzhiyun #define SPI_RBEI 0x20
52*4882a593Smuzhiyun #define SPI_RBFI 0x10
53*4882a593Smuzhiyun #define SPI_SpiS0 0x02
54*4882a593Smuzhiyun #define SPI_SSS 0x01
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* CR7 */
57*4882a593Smuzhiyun #define CR7_IDX_OR12 0x12
58*4882a593Smuzhiyun #define OR12_ADDR32 0x00000001
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
61*4882a593Smuzhiyun #define spi_read(addr) (*(volatile unsigned long *)(addr))
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* M25P80 */
64*4882a593Smuzhiyun #define M25_READ 0x03
65*4882a593Smuzhiyun #define M25_READ_4BYTE 0x13
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun extern void bss_start(void);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
spi_reset(void)70*4882a593Smuzhiyun static void __uses_spiboot2 spi_reset(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun int timeout = 0x00100000;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Make sure the last transaction is finalized */
75*4882a593Smuzhiyun spi_write(0x00, CR3);
76*4882a593Smuzhiyun spi_write(0x02, CR1);
77*4882a593Smuzhiyun while (!(spi_read(CR4) & SPI_SpiS0)) {
78*4882a593Smuzhiyun if (timeout-- < 0)
79*4882a593Smuzhiyun break;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun spi_write(0x00, CR1);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
84*4882a593Smuzhiyun spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun spi_write(0, SPIDMCOR);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
spi_read_flash(void * buf,unsigned long addr,unsigned long len)89*4882a593Smuzhiyun static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
90*4882a593Smuzhiyun unsigned long len)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun spi_write(CR7_IDX_OR12, CR7);
93*4882a593Smuzhiyun if (spi_read(CR8) & OR12_ADDR32) {
94*4882a593Smuzhiyun /* 4-bytes address mode */
95*4882a593Smuzhiyun spi_write(M25_READ_4BYTE, TBR);
96*4882a593Smuzhiyun spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */
97*4882a593Smuzhiyun } else {
98*4882a593Smuzhiyun /* 3-bytes address mode */
99*4882a593Smuzhiyun spi_write(M25_READ, TBR);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */
102*4882a593Smuzhiyun spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */
103*4882a593Smuzhiyun spi_write(addr & 0xFF, TBR); /* ADDR7-0 */
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
106*4882a593Smuzhiyun spi_write((unsigned long)buf, SPIWDMADR);
107*4882a593Smuzhiyun spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
108*4882a593Smuzhiyun spi_write(1, SPIDMCOR);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun spi_write(0xff, CR3);
111*4882a593Smuzhiyun spi_write(spi_read(CR1) | SPI_SSDB, CR1);
112*4882a593Smuzhiyun spi_write(spi_read(CR1) | SPI_SSA, CR1);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
115*4882a593Smuzhiyun ;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Nagate SP0-SS0 */
118*4882a593Smuzhiyun spi_write(0, CR1);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
spiboot_main(void)121*4882a593Smuzhiyun void __uses_spiboot2 spiboot_main(void)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun /*
124*4882a593Smuzhiyun * This code rounds len up for SPIWDMCNTR. We should set it to 0 in
125*4882a593Smuzhiyun * lower 5-bits.
126*4882a593Smuzhiyun */
127*4882a593Smuzhiyun void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
128*4882a593Smuzhiyun volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun spi_reset();
131*4882a593Smuzhiyun spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun _start();
134*4882a593Smuzhiyun }
135