1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012 Renesas Solutions Corp.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU Lesser
5*4882a593Smuzhiyun * General Public License. See the file "COPYING.LIB" in the main
6*4882a593Smuzhiyun * directory of this archive for more details.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
12*4882a593Smuzhiyun #define CONFIG_SPI_ADDR 0x00000000
13*4882a593Smuzhiyun #define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
14*4882a593Smuzhiyun #define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define SPIWDMADR 0xFE001018
17*4882a593Smuzhiyun #define SPIWDMCNTR 0xFE001020
18*4882a593Smuzhiyun #define SPIDMCOR 0xFE001028
19*4882a593Smuzhiyun #define SPIDMINTSR 0xFE001188
20*4882a593Smuzhiyun #define SPIDMINTMR 0xFE001190
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define SPIDMINTSR_DMEND 0x00000004
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define TBR 0xFE002000
25*4882a593Smuzhiyun #define RBR 0xFE002000
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define CR1 0xFE002008
28*4882a593Smuzhiyun #define CR2 0xFE002010
29*4882a593Smuzhiyun #define CR3 0xFE002018
30*4882a593Smuzhiyun #define CR4 0xFE002020
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* CR1 */
33*4882a593Smuzhiyun #define SPI_TBE 0x80
34*4882a593Smuzhiyun #define SPI_TBF 0x40
35*4882a593Smuzhiyun #define SPI_RBE 0x20
36*4882a593Smuzhiyun #define SPI_RBF 0x10
37*4882a593Smuzhiyun #define SPI_PFONRD 0x08
38*4882a593Smuzhiyun #define SPI_SSDB 0x04
39*4882a593Smuzhiyun #define SPI_SSD 0x02
40*4882a593Smuzhiyun #define SPI_SSA 0x01
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* CR2 */
43*4882a593Smuzhiyun #define SPI_RSTF 0x80
44*4882a593Smuzhiyun #define SPI_LOOPBK 0x40
45*4882a593Smuzhiyun #define SPI_CPOL 0x20
46*4882a593Smuzhiyun #define SPI_CPHA 0x10
47*4882a593Smuzhiyun #define SPI_L1M0 0x08
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* CR4 */
50*4882a593Smuzhiyun #define SPI_TBEI 0x80
51*4882a593Smuzhiyun #define SPI_TBFI 0x40
52*4882a593Smuzhiyun #define SPI_RBEI 0x20
53*4882a593Smuzhiyun #define SPI_RBFI 0x10
54*4882a593Smuzhiyun #define SPI_SpiS0 0x02
55*4882a593Smuzhiyun #define SPI_SSS 0x01
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
58*4882a593Smuzhiyun #define spi_read(addr) (*(volatile unsigned long *)(addr))
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* M25P80 */
61*4882a593Smuzhiyun #define M25_READ 0x03
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
spi_reset(void)64*4882a593Smuzhiyun static void __uses_spiboot2 spi_reset(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun int timeout = 0x00100000;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Make sure the last transaction is finalized */
69*4882a593Smuzhiyun spi_write(0x00, CR3);
70*4882a593Smuzhiyun spi_write(0x02, CR1);
71*4882a593Smuzhiyun while (!(spi_read(CR4) & SPI_SpiS0)) {
72*4882a593Smuzhiyun if (timeout-- < 0)
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun spi_write(0x00, CR1);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
78*4882a593Smuzhiyun spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun spi_write(0, SPIDMCOR);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
spi_read_flash(void * buf,unsigned long addr,unsigned long len)83*4882a593Smuzhiyun static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
84*4882a593Smuzhiyun unsigned long len)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun spi_write(M25_READ, TBR);
87*4882a593Smuzhiyun spi_write((addr >> 16) & 0xFF, TBR);
88*4882a593Smuzhiyun spi_write((addr >> 8) & 0xFF, TBR);
89*4882a593Smuzhiyun spi_write(addr & 0xFF, TBR);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
92*4882a593Smuzhiyun spi_write((unsigned long)buf, SPIWDMADR);
93*4882a593Smuzhiyun spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
94*4882a593Smuzhiyun spi_write(1, SPIDMCOR);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun spi_write(0xff, CR3);
97*4882a593Smuzhiyun spi_write(spi_read(CR1) | SPI_SSDB, CR1);
98*4882a593Smuzhiyun spi_write(spi_read(CR1) | SPI_SSA, CR1);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
101*4882a593Smuzhiyun ;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Nagate SP0-SS0 */
104*4882a593Smuzhiyun spi_write(0, CR1);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
spiboot_main(void)107*4882a593Smuzhiyun void __uses_spiboot2 spiboot_main(void)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun spi_reset();
112*4882a593Smuzhiyun spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
113*4882a593Smuzhiyun CONFIG_SPI_LENGTH);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun _start();
116*4882a593Smuzhiyun }
117