1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2012 Renesas Electronics Europe Ltd. 3*4882a593Smuzhiyun * Copyright (C) 2012 Phil Edworthy 4*4882a593Smuzhiyun * Copyright (C) 2008 Renesas Solutions Corp. 5*4882a593Smuzhiyun * Copyright (C) 2008 Nobuhiro Iwamatsu 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on board/renesas/rsk7264/lowlevel_init.S 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun#include <config.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <asm/processor.h> 14*4882a593Smuzhiyun#include <asm/macro.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun .global lowlevel_init 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun .text 19*4882a593Smuzhiyun .align 2 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunlowlevel_init: 22*4882a593Smuzhiyun /* Flush and enable caches (data cache in write-through mode) */ 23*4882a593Smuzhiyun write32 CCR1_A ,CCR1_D 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Disable WDT */ 26*4882a593Smuzhiyun write16 WTCSR_A, WTCSR_D 27*4882a593Smuzhiyun write16 WTCNT_A, WTCNT_D 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Disable Register Bank interrupts */ 30*4882a593Smuzhiyun write16 IBNR_A, IBNR_D 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Set clocks based on 13.225MHz xtal */ 33*4882a593Smuzhiyun write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Enable all peripherals */ 36*4882a593Smuzhiyun write8 STBCR3_A, STBCR3_D 37*4882a593Smuzhiyun write8 STBCR4_A, STBCR4_D 38*4882a593Smuzhiyun write8 STBCR5_A, STBCR5_D 39*4882a593Smuzhiyun write8 STBCR6_A, STBCR6_D 40*4882a593Smuzhiyun write8 STBCR7_A, STBCR7_D 41*4882a593Smuzhiyun write8 STBCR8_A, STBCR8_D 42*4882a593Smuzhiyun write8 STBCR9_A, STBCR9_D 43*4882a593Smuzhiyun write8 STBCR10_A, STBCR10_D 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* SCIF7 and IIC2 */ 46*4882a593Smuzhiyun write16 PJCR3_A, PJCR3_D /* TXD7 */ 47*4882a593Smuzhiyun write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Configure bus (CS0) */ 50*4882a593Smuzhiyun write16 PFCR3_A, PFCR3_D /* A24 */ 51*4882a593Smuzhiyun write16 PFCR2_A, PFCR2_D /* A23 and CS1# */ 52*4882a593Smuzhiyun write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */ 53*4882a593Smuzhiyun write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ 54*4882a593Smuzhiyun write32 CS0WCR_A, CS0WCR_D 55*4882a593Smuzhiyun write32 CS0BCR_A, CS0BCR_D 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Configure SDRAM (CS3) */ 58*4882a593Smuzhiyun write16 PCCR2_A, PCCR2_D /* CS3# */ 59*4882a593Smuzhiyun write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */ 60*4882a593Smuzhiyun write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ 61*4882a593Smuzhiyun write32 CS3BCR_A, CS3BCR_D 62*4882a593Smuzhiyun write32 CS3WCR_A, CS3WCR_D 63*4882a593Smuzhiyun write32 SDCR_A, SDCR_D 64*4882a593Smuzhiyun write32 RTCOR_A, RTCOR_D 65*4882a593Smuzhiyun write32 RTCSR_A, RTCSR_D 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Configure ethernet (CS1) */ 68*4882a593Smuzhiyun write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */ 69*4882a593Smuzhiyun write16 PHCR0_A, PHCR0_D 70*4882a593Smuzhiyun write16 PFCR2_A, PFCR2_D /* CS1# */ 71*4882a593Smuzhiyun write32 CS1BCR_A, CS1BCR_D /* Big endian */ 72*4882a593Smuzhiyun write32 CS1WCR_A, CS1WCR_D /* 1 cycle */ 73*4882a593Smuzhiyun write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */ 74*4882a593Smuzhiyun write16 PJIOR1_A, PJIOR1_D 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* wait 200us */ 77*4882a593Smuzhiyun mov.l REPEAT_D, r3 78*4882a593Smuzhiyun mov #0, r2 79*4882a593Smuzhiyunrepeat0: 80*4882a593Smuzhiyun add #1, r2 81*4882a593Smuzhiyun cmp/hs r3, r2 82*4882a593Smuzhiyun bf repeat0 83*4882a593Smuzhiyun nop 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun mov.l SDRAM_MODE, r1 86*4882a593Smuzhiyun mov #0, r0 87*4882a593Smuzhiyun mov.l r0, @r1 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun nop 90*4882a593Smuzhiyun rts 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun .align 4 93*4882a593Smuzhiyun 94*4882a593SmuzhiyunCCR1_A: .long CCR1 95*4882a593SmuzhiyunCCR1_D: .long 0x0000090B 96*4882a593Smuzhiyun 97*4882a593SmuzhiyunSTBCR3_A: .long 0xFFFE0408 98*4882a593SmuzhiyunSTBCR4_A: .long 0xFFFE040C 99*4882a593SmuzhiyunSTBCR5_A: .long 0xFFFE0410 100*4882a593SmuzhiyunSTBCR6_A: .long 0xFFFE0414 101*4882a593SmuzhiyunSTBCR7_A: .long 0xFFFE0418 102*4882a593SmuzhiyunSTBCR8_A: .long 0xFFFE041C 103*4882a593SmuzhiyunSTBCR9_A: .long 0xFFFE0440 104*4882a593SmuzhiyunSTBCR10_A: .long 0xFFFE0444 105*4882a593SmuzhiyunSTBCR3_D: .long 0x0000001A 106*4882a593SmuzhiyunSTBCR4_D: .long 0x00000000 107*4882a593SmuzhiyunSTBCR5_D: .long 0x00000000 108*4882a593SmuzhiyunSTBCR6_D: .long 0x00000000 109*4882a593SmuzhiyunSTBCR7_D: .long 0x00000012 110*4882a593SmuzhiyunSTBCR8_D: .long 0x00000009 111*4882a593SmuzhiyunSTBCR9_D: .long 0x00000000 112*4882a593SmuzhiyunSTBCR10_D: .long 0x00000010 113*4882a593Smuzhiyun 114*4882a593SmuzhiyunWTCSR_A: .long 0xFFFE0000 115*4882a593SmuzhiyunWTCNT_A: .long 0xFFFE0002 116*4882a593SmuzhiyunWTCSR_D: .word 0xA518 117*4882a593SmuzhiyunWTCNT_D: .word 0x5A00 118*4882a593Smuzhiyun 119*4882a593SmuzhiyunIBNR_A: .long 0xFFFE080E 120*4882a593SmuzhiyunIBNR_D: .word 0x0000 121*4882a593Smuzhiyun.align 2 122*4882a593SmuzhiyunFRQCR_A: .long 0xFFFE0010 123*4882a593SmuzhiyunFRQCR_D: .word 0x0015 124*4882a593Smuzhiyun.align 2 125*4882a593Smuzhiyun 126*4882a593SmuzhiyunPJCR3_A: .long 0xFFFE3908 127*4882a593SmuzhiyunPJCR3_D: .word 0x5000 128*4882a593Smuzhiyun.align 2 129*4882a593SmuzhiyunPECR1_A: .long 0xFFFE388C 130*4882a593SmuzhiyunPECR1_D: .word 0x2011 131*4882a593Smuzhiyun.align 2 132*4882a593Smuzhiyun 133*4882a593SmuzhiyunPFCR3_A: .long 0xFFFE38A8 134*4882a593SmuzhiyunPFCR2_A: .long 0xFFFE38AA 135*4882a593SmuzhiyunPBCR5_A: .long 0xFFFE3824 136*4882a593SmuzhiyunPFCR3_D: .word 0x0010 137*4882a593SmuzhiyunPFCR2_D: .word 0x0101 138*4882a593SmuzhiyunPBCR5_D: .word 0x0111 139*4882a593Smuzhiyun.align 2 140*4882a593SmuzhiyunCS0WCR_A: .long 0xFFFC0028 141*4882a593SmuzhiyunCS0WCR_D: .long 0x00000341 142*4882a593SmuzhiyunCS0BCR_A: .long 0xFFFC0004 143*4882a593SmuzhiyunCS0BCR_D: .long 0x00000400 144*4882a593Smuzhiyun 145*4882a593SmuzhiyunPCCR2_A: .long 0xFFFE384A 146*4882a593SmuzhiyunPCCR1_A: .long 0xFFFE384C 147*4882a593SmuzhiyunPCCR0_A: .long 0xFFFE384E 148*4882a593SmuzhiyunPCCR2_D: .word 0x0001 149*4882a593SmuzhiyunPCCR1_D: .word 0x1111 150*4882a593SmuzhiyunPCCR0_D: .word 0x1111 151*4882a593Smuzhiyun.align 2 152*4882a593SmuzhiyunCS3BCR_A: .long 0xFFFC0010 153*4882a593SmuzhiyunCS3BCR_D: .long 0x00004400 154*4882a593SmuzhiyunCS3WCR_A: .long 0xFFFC0034 155*4882a593SmuzhiyunCS3WCR_D: .long 0x00004912 156*4882a593SmuzhiyunSDCR_A: .long 0xFFFC004C 157*4882a593SmuzhiyunSDCR_D: .long 0x00000811 158*4882a593SmuzhiyunRTCOR_A: .long 0xFFFC0058 159*4882a593SmuzhiyunRTCOR_D: .long 0xA55A0035 160*4882a593SmuzhiyunRTCSR_A: .long 0xFFFC0050 161*4882a593SmuzhiyunRTCSR_D: .long 0xA55A0010 162*4882a593Smuzhiyun.align 2 163*4882a593SmuzhiyunSDRAM_MODE: .long 0xFFFC5460 164*4882a593SmuzhiyunREPEAT_D: .long 0x000033F1 165*4882a593Smuzhiyun 166*4882a593SmuzhiyunPHCR1_A: .long 0xFFFE38EC 167*4882a593SmuzhiyunPHCR0_A: .long 0xFFFE38EE 168*4882a593SmuzhiyunPHCR1_D: .word 0x2222 169*4882a593SmuzhiyunPHCR0_D: .word 0x2222 170*4882a593Smuzhiyun.align 2 171*4882a593SmuzhiyunCS1BCR_A: .long 0xFFFC0008 172*4882a593SmuzhiyunCS1BCR_D: .long 0x00000400 173*4882a593SmuzhiyunCS1WCR_A: .long 0xFFFC002C 174*4882a593SmuzhiyunCS1WCR_D: .long 0x00000080 175*4882a593SmuzhiyunPJDR1_A: .long 0xFFFE3914 176*4882a593SmuzhiyunPJDR1_D: .word 0x0000 177*4882a593Smuzhiyun.align 2 178*4882a593SmuzhiyunPJIOR1_A: .long 0xFFFE3910 179*4882a593SmuzhiyunPJIOR1_D: .word 0x8000 180*4882a593Smuzhiyun.align 2 181