1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2011 Renesas Electronics Europe Ltd. 3*4882a593Smuzhiyun * Copyright (C) 2008 Renesas Solutions Corp. 4*4882a593Smuzhiyun * Copyright (C) 2008 Nobuhiro Iwamatsu 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on board/renesas/rsk7203/lowlevel_init.S 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun#include <config.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include <asm/processor.h> 13*4882a593Smuzhiyun#include <asm/macro.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun .global lowlevel_init 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun .text 18*4882a593Smuzhiyun .align 2 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunlowlevel_init: 21*4882a593Smuzhiyun /* Cache setting */ 22*4882a593Smuzhiyun write32 CCR1_A ,CCR1_D 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* io_set_cpg */ 25*4882a593Smuzhiyun write8 STBCR3_A, STBCR3_D 26*4882a593Smuzhiyun write8 STBCR4_A, STBCR4_D 27*4882a593Smuzhiyun write8 STBCR5_A, STBCR5_D 28*4882a593Smuzhiyun write8 STBCR6_A, STBCR6_D 29*4882a593Smuzhiyun write8 STBCR7_A, STBCR7_D 30*4882a593Smuzhiyun write8 STBCR8_A, STBCR8_D 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* ConfigurePortPins */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Leaving LED1 ON for sanity test */ 35*4882a593Smuzhiyun write16 PJCR1_A, PJCR1_D1 36*4882a593Smuzhiyun write16 PJCR2_A, PJCR2_D 37*4882a593Smuzhiyun write16 PJIOR0_A, PJIOR0_D1 38*4882a593Smuzhiyun write16 PJDR0_A, PJDR0_D 39*4882a593Smuzhiyun write16 PJPR0_A, PJPR0_D 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Configure EN_PIN & RS_PIN */ 42*4882a593Smuzhiyun write16 PGCR2_A, PGCR2_D 43*4882a593Smuzhiyun write16 PGIOR0_A, PGIOR0_D 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Configure the port pins connected to UART */ 46*4882a593Smuzhiyun write16 PJCR1_A, PJCR1_D2 47*4882a593Smuzhiyun write16 PJIOR0_A, PJIOR0_D2 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Configure Operating Frequency */ 50*4882a593Smuzhiyun write16 WTCSR_A, WTCSR_D0 51*4882a593Smuzhiyun write16 WTCSR_A, WTCSR_D1 52*4882a593Smuzhiyun write16 WTCNT_A, WTCNT_D 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Control of RESBANK */ 55*4882a593Smuzhiyun write16 IBNR_A, IBNR_D 56*4882a593Smuzhiyun /* Enable SCIF3 module */ 57*4882a593Smuzhiyun write16 STBCR4_A, STBCR4_D 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Set clock mode*/ 60*4882a593Smuzhiyun write16 FRQCR_A, FRQCR_D 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Configure Bus And Memory */ 63*4882a593Smuzhiyuninit_bsc_cs0: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunpfc_settings: 66*4882a593Smuzhiyun write16 PCCR2_A, PCCR2_D 67*4882a593Smuzhiyun write16 PCCR1_A, PCCR1_D 68*4882a593Smuzhiyun write16 PCCR0_A, PCCR0_D 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun write16 PBCR0_A, PBCR0_D 71*4882a593Smuzhiyun write16 PBCR1_A, PBCR1_D 72*4882a593Smuzhiyun write16 PBCR2_A, PBCR2_D 73*4882a593Smuzhiyun write16 PBCR3_A, PBCR3_D 74*4882a593Smuzhiyun write16 PBCR4_A, PBCR4_D 75*4882a593Smuzhiyun write16 PBCR5_A, PBCR5_D 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun write16 PDCR0_A, PDCR0_D 78*4882a593Smuzhiyun write16 PDCR1_A, PDCR1_D 79*4882a593Smuzhiyun write16 PDCR2_A, PDCR2_D 80*4882a593Smuzhiyun write16 PDCR3_A, PDCR3_D 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun write32 CS0WCR_A, CS0WCR_D 83*4882a593Smuzhiyun write32 CS0BCR_A, CS0BCR_D 84*4882a593Smuzhiyun 85*4882a593Smuzhiyuninit_bsc_cs2: 86*4882a593Smuzhiyun write16 PJCR0_A, PJCR0_D 87*4882a593Smuzhiyun write32 CS2WCR_A, CS2WCR_D 88*4882a593Smuzhiyun 89*4882a593Smuzhiyuninit_sdram: 90*4882a593Smuzhiyun write32 CS3BCR_A, CS3BCR_D 91*4882a593Smuzhiyun write32 CS3WCR_A, CS3WCR_D 92*4882a593Smuzhiyun write32 SDCR_A, SDCR_D 93*4882a593Smuzhiyun write32 RTCOR_A, RTCOR_D 94*4882a593Smuzhiyun write32 RTCSR_A, RTCSR_D 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* wait 200us */ 97*4882a593Smuzhiyun mov.l REPEAT_D, r3 98*4882a593Smuzhiyun mov #0, r2 99*4882a593Smuzhiyunrepeat0: 100*4882a593Smuzhiyun add #1, r2 101*4882a593Smuzhiyun cmp/hs r3, r2 102*4882a593Smuzhiyun bf repeat0 103*4882a593Smuzhiyun nop 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun mov.l SDRAM_MODE, r1 106*4882a593Smuzhiyun mov #0, r0 107*4882a593Smuzhiyun mov.l r0, @r1 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun nop 110*4882a593Smuzhiyun rts 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun .align 4 113*4882a593Smuzhiyun 114*4882a593SmuzhiyunCCR1_A: .long CCR1 115*4882a593SmuzhiyunCCR1_D: .long 0x0000090B 116*4882a593SmuzhiyunFRQCR_A: .long 0xFFFE0010 117*4882a593SmuzhiyunFRQCR_D: .word 0x1003 118*4882a593Smuzhiyun.align 2 119*4882a593SmuzhiyunSTBCR3_A: .long 0xFFFE0408 120*4882a593SmuzhiyunSTBCR3_D: .long 0x00000002 121*4882a593SmuzhiyunSTBCR4_A: .long 0xFFFE040C 122*4882a593SmuzhiyunSTBCR4_D: .word 0x0000 123*4882a593Smuzhiyun.align 2 124*4882a593SmuzhiyunSTBCR5_A: .long 0xFFFE0410 125*4882a593SmuzhiyunSTBCR5_D: .long 0x00000010 126*4882a593SmuzhiyunSTBCR6_A: .long 0xFFFE0414 127*4882a593SmuzhiyunSTBCR6_D: .long 0x00000002 128*4882a593SmuzhiyunSTBCR7_A: .long 0xFFFE0418 129*4882a593SmuzhiyunSTBCR7_D: .long 0x0000002A 130*4882a593SmuzhiyunSTBCR8_A: .long 0xFFFE041C 131*4882a593SmuzhiyunSTBCR8_D: .long 0x0000007E 132*4882a593SmuzhiyunPJCR1_A: .long 0xFFFE390C 133*4882a593SmuzhiyunPJCR1_D1: .word 0x0000 134*4882a593SmuzhiyunPJCR1_D2: .word 0x0022 135*4882a593SmuzhiyunPJCR2_A: .long 0xFFFE390A 136*4882a593SmuzhiyunPJCR2_D: .word 0x0000 137*4882a593Smuzhiyun.align 2 138*4882a593SmuzhiyunPJIOR0_A: .long 0xFFFE3912 139*4882a593SmuzhiyunPJIOR0_D1: .word 0x0FC0 140*4882a593SmuzhiyunPJIOR0_D2: .word 0x0FE0 141*4882a593SmuzhiyunPJDR0_A: .long 0xFFFE3916 142*4882a593SmuzhiyunPJDR0_D: .word 0x0FBF 143*4882a593Smuzhiyun.align 2 144*4882a593SmuzhiyunPJPR0_A: .long 0xFFFE391A 145*4882a593SmuzhiyunPJPR0_D: .long 0x00000FBF 146*4882a593SmuzhiyunPGCR2_A: .long 0xFFFE38CA 147*4882a593SmuzhiyunPGCR2_D: .word 0x0000 148*4882a593Smuzhiyun.align 2 149*4882a593SmuzhiyunPGIOR0_A: .long 0xFFFE38D2 150*4882a593SmuzhiyunPGIOR0_D: .word 0x03F0 151*4882a593Smuzhiyun.align 2 152*4882a593SmuzhiyunWTCSR_A: .long 0xFFFE0000 153*4882a593SmuzhiyunWTCSR_D0: .word 0x0000 154*4882a593SmuzhiyunWTCSR_D1: .word 0x0000 155*4882a593SmuzhiyunWTCNT_A: .long 0xFFFE0002 156*4882a593SmuzhiyunWTCNT_D: .word 0x0000 157*4882a593Smuzhiyun.align 2 158*4882a593SmuzhiyunPCCR0_A: .long 0xFFFE384E 159*4882a593SmuzhiyunPDCR0_A: .long 0xFFFE386E 160*4882a593SmuzhiyunPDCR1_A: .long 0xFFFE386C 161*4882a593SmuzhiyunPDCR2_A: .long 0xFFFE386A 162*4882a593SmuzhiyunPDCR3_A: .long 0xFFFE3868 163*4882a593SmuzhiyunPBCR0_A: .long 0xFFFE382E 164*4882a593SmuzhiyunPBCR1_A: .long 0xFFFE382C 165*4882a593SmuzhiyunPBCR2_A: .long 0xFFFE382A 166*4882a593SmuzhiyunPBCR3_A: .long 0xFFFE3828 167*4882a593SmuzhiyunPBCR4_A: .long 0xFFFE3826 168*4882a593SmuzhiyunPBCR5_A: .long 0xFFFE3824 169*4882a593SmuzhiyunPCCR0_D: .word 0x1111 170*4882a593SmuzhiyunPDCR0_D: .word 0x1111 171*4882a593SmuzhiyunPDCR1_D: .word 0x1111 172*4882a593SmuzhiyunPDCR2_D: .word 0x1111 173*4882a593SmuzhiyunPDCR3_D: .word 0x1111 174*4882a593SmuzhiyunPBCR0_D: .word 0x1110 175*4882a593SmuzhiyunPBCR1_D: .word 0x1111 176*4882a593SmuzhiyunPBCR2_D: .word 0x1111 177*4882a593SmuzhiyunPBCR3_D: .word 0x1111 178*4882a593SmuzhiyunPBCR4_D: .word 0x1111 179*4882a593SmuzhiyunPBCR5_D: .word 0x0111 180*4882a593Smuzhiyun.align 2 181*4882a593SmuzhiyunCS0WCR_A: .long 0xFFFC0028 182*4882a593SmuzhiyunCS0WCR_D: .long 0x00000B41 183*4882a593SmuzhiyunCS0BCR_A: .long 0xFFFC0004 184*4882a593SmuzhiyunCS0BCR_D: .long 0x10000400 185*4882a593SmuzhiyunPJCR0_A: .long 0xFFFE390E 186*4882a593SmuzhiyunPJCR0_D: .word 0x3300 187*4882a593Smuzhiyun.align 2 188*4882a593SmuzhiyunCS2WCR_A: .long 0xFFFC0030 189*4882a593SmuzhiyunCS2WCR_D: .long 0x00000B01 190*4882a593SmuzhiyunPCCR2_A: .long 0xFFFE384A 191*4882a593SmuzhiyunPCCR2_D: .word 0x0001 192*4882a593Smuzhiyun.align 2 193*4882a593SmuzhiyunPCCR1_A: .long 0xFFFE384C 194*4882a593SmuzhiyunPCCR1_D: .word 0x1111 195*4882a593Smuzhiyun.align 2 196*4882a593SmuzhiyunCS3BCR_A: .long 0xFFFC0010 197*4882a593SmuzhiyunCS3BCR_D: .long 0x00004400 198*4882a593SmuzhiyunCS3WCR_A: .long 0xFFFC0034 199*4882a593SmuzhiyunCS3WCR_D: .long 0x0000288A 200*4882a593SmuzhiyunSDCR_A: .long 0xFFFC004C 201*4882a593SmuzhiyunSDCR_D: .long 0x00000812 202*4882a593SmuzhiyunRTCOR_A: .long 0xFFFC0058 203*4882a593SmuzhiyunRTCOR_D: .long 0xA55A0046 204*4882a593SmuzhiyunRTCSR_A: .long 0xFFFC0050 205*4882a593SmuzhiyunRTCSR_D: .long 0xA55A0010 206*4882a593SmuzhiyunIBNR_A: .long 0xFFFE080E 207*4882a593SmuzhiyunIBNR_D: .word 0x0000 208*4882a593Smuzhiyun.align 2 209*4882a593SmuzhiyunSDRAM_MODE: .long 0xFFFC5040 210*4882a593SmuzhiyunREPEAT_D: .long 0x00000085 211