1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * board/renesas/rcar-common/common.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Renesas Electronics Corporation
5*4882a593Smuzhiyun * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
6*4882a593Smuzhiyun * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
14*4882a593Smuzhiyun #include <asm/arch/rmobile.h>
15*4882a593Smuzhiyun #include <asm/arch/rcar-mstp.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define TSTR0 0x04
18*4882a593Smuzhiyun #define TSTR0_STR0 0x01
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static struct mstp_ctl mstptbl[] = {
21*4882a593Smuzhiyun { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
22*4882a593Smuzhiyun RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
23*4882a593Smuzhiyun { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
24*4882a593Smuzhiyun RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
25*4882a593Smuzhiyun { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
26*4882a593Smuzhiyun RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
27*4882a593Smuzhiyun { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
28*4882a593Smuzhiyun RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
29*4882a593Smuzhiyun { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
30*4882a593Smuzhiyun RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
31*4882a593Smuzhiyun { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
32*4882a593Smuzhiyun RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
33*4882a593Smuzhiyun #ifdef CONFIG_RCAR_GEN3
34*4882a593Smuzhiyun { SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
35*4882a593Smuzhiyun RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
36*4882a593Smuzhiyun #endif
37*4882a593Smuzhiyun { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
38*4882a593Smuzhiyun RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
39*4882a593Smuzhiyun { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
40*4882a593Smuzhiyun RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
41*4882a593Smuzhiyun { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
42*4882a593Smuzhiyun RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
43*4882a593Smuzhiyun { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
44*4882a593Smuzhiyun RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
45*4882a593Smuzhiyun { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
46*4882a593Smuzhiyun RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
arch_preboot_os(void)49*4882a593Smuzhiyun void arch_preboot_os(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun int i;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* stop TMU0 */
54*4882a593Smuzhiyun mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Stop module clock */
57*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
58*4882a593Smuzhiyun mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr,
59*4882a593Smuzhiyun mstptbl[i].s_dis,
60*4882a593Smuzhiyun mstptbl[i].s_ena);
61*4882a593Smuzhiyun mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr,
62*4882a593Smuzhiyun mstptbl[i].r_dis,
63*4882a593Smuzhiyun mstptbl[i].r_ena);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun }
66