1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2007 Nobuhiro Iwamatsu 3*4882a593Smuzhiyun * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * u-boot/board/r7780mp/r7780mp.h 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _BOARD_R7780MP_R7780MP_H_ 11*4882a593Smuzhiyun #define _BOARD_R7780MP_R7780MP_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* R7780MP's FPGA register map */ 14*4882a593Smuzhiyun #define FPGA_BASE 0xa4000000 15*4882a593Smuzhiyun #define FPGA_IRLMSK (FPGA_BASE + 0x00) 16*4882a593Smuzhiyun #define FPGA_IRLMON (FPGA_BASE + 0x02) 17*4882a593Smuzhiyun #define FPGA_IRLPRI1 (FPGA_BASE + 0x04) 18*4882a593Smuzhiyun #define FPGA_IRLPRI2 (FPGA_BASE + 0x06) 19*4882a593Smuzhiyun #define FPGA_IRLPRI3 (FPGA_BASE + 0x08) 20*4882a593Smuzhiyun #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) 21*4882a593Smuzhiyun #define FPGA_RSTCTL (FPGA_BASE + 0x0C) 22*4882a593Smuzhiyun #define FPGA_PCIBD (FPGA_BASE + 0x0E) 23*4882a593Smuzhiyun #define FPGA_PCICD (FPGA_BASE + 0x10) 24*4882a593Smuzhiyun #define FPGA_EXTGIO (FPGA_BASE + 0x16) 25*4882a593Smuzhiyun #define FPGA_IVDRMON (FPGA_BASE + 0x18) 26*4882a593Smuzhiyun #define FPGA_IVDRCR (FPGA_BASE + 0x1A) 27*4882a593Smuzhiyun #define FPGA_OBLED (FPGA_BASE + 0x1C) 28*4882a593Smuzhiyun #define FPGA_OBSW (FPGA_BASE + 0x1E) 29*4882a593Smuzhiyun #define FPGA_TPCTL (FPGA_BASE + 0x100) 30*4882a593Smuzhiyun #define FPGA_TPDCKCTL (FPGA_BASE + 0x102) 31*4882a593Smuzhiyun #define FPGA_TPCLR (FPGA_BASE + 0x104) 32*4882a593Smuzhiyun #define FPGA_TPXPOS (FPGA_BASE + 0x106) 33*4882a593Smuzhiyun #define FPGA_TPYPOS (FPGA_BASE + 0x108) 34*4882a593Smuzhiyun #define FPGA_DBSW (FPGA_BASE + 0x200) 35*4882a593Smuzhiyun #define FPGA_VERSION (FPGA_BASE + 0x700) 36*4882a593Smuzhiyun #define FPGA_CFCTL (FPGA_BASE + 0x300) 37*4882a593Smuzhiyun #define FPGA_CFPOW (FPGA_BASE + 0x302) 38*4882a593Smuzhiyun #define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) 39*4882a593Smuzhiyun #define FPGA_PMR (FPGA_BASE + 0x900) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* _BOARD_R7780RP_R7780RP_H_ */ 42