1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2008 Renesas Solutions Corp.
3*4882a593Smuzhiyun * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <netdev.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/processor.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /* PRI control register */
14*4882a593Smuzhiyun #define PRPRICR5 0xFF800048 /* LMB */
15*4882a593Smuzhiyun #define PRPRICR5_D 0x2a
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* FPGA control */
18*4882a593Smuzhiyun #define FPGA_NAND_CTL 0xB410020C
19*4882a593Smuzhiyun #define FPGA_NAND_RST 0x0008
20*4882a593Smuzhiyun #define FPGA_NAND_INIT 0x0000
21*4882a593Smuzhiyun #define FPGA_NAND_RST_WAIT 10000
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* I/O port data */
24*4882a593Smuzhiyun #define PACR_D 0x0000
25*4882a593Smuzhiyun #define PBCR_D 0x0000
26*4882a593Smuzhiyun #define PCCR_D 0x1000
27*4882a593Smuzhiyun #define PDCR_D 0x0000
28*4882a593Smuzhiyun #define PECR_D 0x0410
29*4882a593Smuzhiyun #define PFCR_D 0xffff
30*4882a593Smuzhiyun #define PGCR_D 0x0000
31*4882a593Smuzhiyun #define PHCR_D 0x5011
32*4882a593Smuzhiyun #define PJCR_D 0x4400
33*4882a593Smuzhiyun #define PKCR_D 0x7c00
34*4882a593Smuzhiyun #define PLCR_D 0x0000
35*4882a593Smuzhiyun #define PMCR_D 0x0000
36*4882a593Smuzhiyun #define PNCR_D 0x0000
37*4882a593Smuzhiyun #define PQCR_D 0x0000
38*4882a593Smuzhiyun #define PRCR_D 0x0000
39*4882a593Smuzhiyun #define PSCR_D 0x0000
40*4882a593Smuzhiyun #define PTCR_D 0x0010
41*4882a593Smuzhiyun #define PUCR_D 0x0fff
42*4882a593Smuzhiyun #define PVCR_D 0xffff
43*4882a593Smuzhiyun #define PWCR_D 0x0000
44*4882a593Smuzhiyun #define PXCR_D 0x7500
45*4882a593Smuzhiyun #define PYCR_D 0x0000
46*4882a593Smuzhiyun #define PZCR_D 0x5540
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Pin Function Controler data */
49*4882a593Smuzhiyun #define PSELA_D 0x1410
50*4882a593Smuzhiyun #define PSELB_D 0x0140
51*4882a593Smuzhiyun #define PSELC_D 0x0000
52*4882a593Smuzhiyun #define PSELD_D 0x0400
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* I/O Buffer Hi-Z data */
55*4882a593Smuzhiyun #define HIZCRA_D 0x0000
56*4882a593Smuzhiyun #define HIZCRB_D 0x1000
57*4882a593Smuzhiyun #define HIZCRC_D 0x0000
58*4882a593Smuzhiyun #define HIZCRD_D 0x0000
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Module select reg data */
61*4882a593Smuzhiyun #define MSELCRA_D 0x0014
62*4882a593Smuzhiyun #define MSELCRB_D 0x0018
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Module Stop reg Data */
65*4882a593Smuzhiyun #define MSTPCR2_D 0xFFD9F280
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* CPLD loader */
68*4882a593Smuzhiyun extern void init_cpld(void);
69*4882a593Smuzhiyun
checkboard(void)70*4882a593Smuzhiyun int checkboard(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun puts("BOARD: AP325RXA\n");
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
board_init(void)76*4882a593Smuzhiyun int board_init(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun /* Pin Function Controler Init */
79*4882a593Smuzhiyun outw(PSELA_D, PSELA);
80*4882a593Smuzhiyun outw(PSELB_D, PSELB);
81*4882a593Smuzhiyun outw(PSELC_D, PSELC);
82*4882a593Smuzhiyun outw(PSELD_D, PSELD);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* I/O Buffer Hi-Z Init */
85*4882a593Smuzhiyun outw(HIZCRA_D, HIZCRA);
86*4882a593Smuzhiyun outw(HIZCRB_D, HIZCRB);
87*4882a593Smuzhiyun outw(HIZCRC_D, HIZCRC);
88*4882a593Smuzhiyun outw(HIZCRD_D, HIZCRD);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Module select reg Init */
91*4882a593Smuzhiyun outw(MSELCRA_D, MSELCRA);
92*4882a593Smuzhiyun outw(MSELCRB_D, MSELCRB);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Module Stop reg Init */
95*4882a593Smuzhiyun outl(MSTPCR2_D, MSTPCR2);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* I/O ports */
98*4882a593Smuzhiyun outw(PACR_D, PACR);
99*4882a593Smuzhiyun outw(PBCR_D, PBCR);
100*4882a593Smuzhiyun outw(PCCR_D, PCCR);
101*4882a593Smuzhiyun outw(PDCR_D, PDCR);
102*4882a593Smuzhiyun outw(PECR_D, PECR);
103*4882a593Smuzhiyun outw(PFCR_D, PFCR);
104*4882a593Smuzhiyun outw(PGCR_D, PGCR);
105*4882a593Smuzhiyun outw(PHCR_D, PHCR);
106*4882a593Smuzhiyun outw(PJCR_D, PJCR);
107*4882a593Smuzhiyun outw(PKCR_D, PKCR);
108*4882a593Smuzhiyun outw(PLCR_D, PLCR);
109*4882a593Smuzhiyun outw(PMCR_D, PMCR);
110*4882a593Smuzhiyun outw(PNCR_D, PNCR);
111*4882a593Smuzhiyun outw(PQCR_D, PQCR);
112*4882a593Smuzhiyun outw(PRCR_D, PRCR);
113*4882a593Smuzhiyun outw(PSCR_D, PSCR);
114*4882a593Smuzhiyun outw(PTCR_D, PTCR);
115*4882a593Smuzhiyun outw(PUCR_D, PUCR);
116*4882a593Smuzhiyun outw(PVCR_D, PVCR);
117*4882a593Smuzhiyun outw(PWCR_D, PWCR);
118*4882a593Smuzhiyun outw(PXCR_D, PXCR);
119*4882a593Smuzhiyun outw(PYCR_D, PYCR);
120*4882a593Smuzhiyun outw(PZCR_D, PZCR);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* PRI control register Init */
123*4882a593Smuzhiyun outl(PRPRICR5_D, PRPRICR5);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* cpld init */
126*4882a593Smuzhiyun init_cpld();
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return 0;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
led_set_state(unsigned short value)131*4882a593Smuzhiyun void led_set_state(unsigned short value)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
ide_set_reset(int idereset)135*4882a593Smuzhiyun void ide_set_reset(int idereset)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
138*4882a593Smuzhiyun udelay(FPGA_NAND_RST_WAIT);
139*4882a593Smuzhiyun outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
board_eth_init(bd_t * bis)142*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun int rc = 0;
145*4882a593Smuzhiyun #ifdef CONFIG_SMC911X
146*4882a593Smuzhiyun rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
147*4882a593Smuzhiyun #endif
148*4882a593Smuzhiyun return rc;
149*4882a593Smuzhiyun }
150