1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2007-2008 3*4882a593Smuzhiyun * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 6*4882a593Smuzhiyun * Kenati Technologies, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * board/MigoR/lowlevel_init.S 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <config.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun#include <asm/processor.h> 16*4882a593Smuzhiyun#include <asm/macro.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/* 19*4882a593Smuzhiyun * Board specific low level init code, called _very_ early in the 20*4882a593Smuzhiyun * startup sequence. Relocation to SDRAM has not happened yet, no 21*4882a593Smuzhiyun * stack is available, bss section has not been initialised, etc. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * (Note: As no stack is available, no subroutines can be called...). 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun .global lowlevel_init 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun .text 29*4882a593Smuzhiyun .align 2 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunlowlevel_init: 32*4882a593Smuzhiyun write32 CCR_A, CCR_D ! Address of Cache Control Register 33*4882a593Smuzhiyun ! Instruction Cache Invalidate 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register 36*4882a593Smuzhiyun ! TI == TLB Invalidate bit 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun write16 PFC_PULCR_A, PFC_PULCR_D 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun write16 PFC_DRVCR_A, PFC_DRVCR_D 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun write16 SBSCR_A, SBSCR_D 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun write16 PSCR_A, PSCR_D 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) 51*4882a593Smuzhiyun ! 0xA507 -> timer_STOP / WDT_CLK = max 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) 54*4882a593Smuzhiyun ! 0x5A00 -> Clear 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) 57*4882a593Smuzhiyun ! 0xA504 -> timer_STOP / CLK = 500ms 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun write32 DLLFRQ_A, DLLFRQ_D ! 20080115 60*4882a593Smuzhiyun ! 20080115 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register 63*4882a593Smuzhiyun ! 20080115 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun write32 CCR_A, CCR_D_2 ! Address of Cache Control Register 66*4882a593Smuzhiyun ! ?? 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunbsc_init: 69*4882a593Smuzhiyun write32 CMNCR_A, CMNCR_D 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun write32 CS0BCR_A, CS0BCR_D 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun write32 CS4BCR_A, CS4BCR_D 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun write32 CS5ABCR_A, CS5ABCR_D 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun write32 CS5BBCR_A, CS5BBCR_D 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun write32 CS6ABCR_A, CS6ABCR_D 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun write32 CS0WCR_A, CS0WCR_D 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun write32 CS4WCR_A, CS4WCR_D 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun write32 CS5AWCR_A, CS5AWCR_D 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun write32 CS5BWCR_A, CS5BWCR_D 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun write32 CS6AWCR_A, CS6AWCR_D 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun ! SDRAM initialization 92*4882a593Smuzhiyun write32 SDCR_A, SDCR_D 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun write32 SDWCR_A, SDWCR_D 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun write32 SDPCR_A, SDPCR_D 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun write32 RTCOR_A, RTCOR_D 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun write32 RTCNT_A, RTCNT_D 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun write32 RTCSR_A, RTCSR_D 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun write32 RFCR_A, RFCR_D 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun write8 SDMR3_A, SDMR3_D 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun ! BL bit off (init = ON) (?!?) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun stc sr, r0 ! BL bit off(init=ON) 111*4882a593Smuzhiyun mov.l SR_MASK_D, r1 112*4882a593Smuzhiyun and r1, r0 113*4882a593Smuzhiyun ldc r0, sr 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun rts 116*4882a593Smuzhiyun mov #0, r0 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun .align 4 119*4882a593Smuzhiyun 120*4882a593SmuzhiyunCCR_A: .long CCR 121*4882a593SmuzhiyunMMUCR_A: .long MMUCR 122*4882a593SmuzhiyunMSTPCR0_A: .long MSTPCR0 123*4882a593SmuzhiyunMSTPCR2_A: .long MSTPCR2 124*4882a593SmuzhiyunPFC_PULCR_A: .long PULCR 125*4882a593SmuzhiyunPFC_DRVCR_A: .long DRVCR 126*4882a593SmuzhiyunSBSCR_A: .long SBSCR 127*4882a593SmuzhiyunPSCR_A: .long PSCR 128*4882a593SmuzhiyunRWTCSR_A: .long RWTCSR 129*4882a593SmuzhiyunRWTCNT_A: .long RWTCNT 130*4882a593SmuzhiyunFRQCR_A: .long FRQCR 131*4882a593SmuzhiyunPLLCR_A: .long PLLCR 132*4882a593SmuzhiyunDLLFRQ_A: .long DLLFRQ 133*4882a593Smuzhiyun 134*4882a593SmuzhiyunCCR_D: .long 0x00000800 135*4882a593SmuzhiyunCCR_D_2: .long 0x00000103 136*4882a593SmuzhiyunMMUCR_D: .long 0x00000004 137*4882a593SmuzhiyunMSTPCR0_D: .long 0x00001001 138*4882a593SmuzhiyunMSTPCR2_D: .long 0xffffffff 139*4882a593SmuzhiyunPFC_PULCR_D: .long 0x6000 140*4882a593SmuzhiyunPFC_DRVCR_D: .long 0x0464 141*4882a593SmuzhiyunFRQCR_D: .long 0x07033639 142*4882a593SmuzhiyunPLLCR_D: .long 0x00005000 143*4882a593SmuzhiyunDLLFRQ_D: .long 0x000004F6 144*4882a593Smuzhiyun 145*4882a593SmuzhiyunCMNCR_A: .long CMNCR 146*4882a593SmuzhiyunCMNCR_D: .long 0x0000001B 147*4882a593SmuzhiyunCS0BCR_A: .long CS0BCR 148*4882a593SmuzhiyunCS0BCR_D: .long 0x24920400 149*4882a593SmuzhiyunCS4BCR_A: .long CS4BCR 150*4882a593SmuzhiyunCS4BCR_D: .long 0x00003400 151*4882a593SmuzhiyunCS5ABCR_A: .long CS5ABCR 152*4882a593SmuzhiyunCS5ABCR_D: .long 0x24920400 153*4882a593SmuzhiyunCS5BBCR_A: .long CS5BBCR 154*4882a593SmuzhiyunCS5BBCR_D: .long 0x24920400 155*4882a593SmuzhiyunCS6ABCR_A: .long CS6ABCR 156*4882a593SmuzhiyunCS6ABCR_D: .long 0x24920400 157*4882a593Smuzhiyun 158*4882a593SmuzhiyunCS0WCR_A: .long CS0WCR 159*4882a593SmuzhiyunCS0WCR_D: .long 0x00000380 160*4882a593SmuzhiyunCS4WCR_A: .long CS4WCR 161*4882a593SmuzhiyunCS4WCR_D: .long 0x00110080 162*4882a593SmuzhiyunCS5AWCR_A: .long CS5AWCR 163*4882a593SmuzhiyunCS5AWCR_D: .long 0x00000300 164*4882a593SmuzhiyunCS5BWCR_A: .long CS5BWCR 165*4882a593SmuzhiyunCS5BWCR_D: .long 0x00000300 166*4882a593SmuzhiyunCS6AWCR_A: .long CS6AWCR 167*4882a593SmuzhiyunCS6AWCR_D: .long 0x00000300 168*4882a593Smuzhiyun 169*4882a593SmuzhiyunSDCR_A: .long SBSC_SDCR 170*4882a593SmuzhiyunSDCR_D: .long 0x80160809 171*4882a593SmuzhiyunSDWCR_A: .long SBSC_SDWCR 172*4882a593SmuzhiyunSDWCR_D: .long 0x0014450C 173*4882a593SmuzhiyunSDPCR_A: .long SBSC_SDPCR 174*4882a593SmuzhiyunSDPCR_D: .long 0x00000087 175*4882a593SmuzhiyunRTCOR_A: .long SBSC_RTCOR 176*4882a593SmuzhiyunRTCNT_A: .long SBSC_RTCNT 177*4882a593SmuzhiyunRTCNT_D: .long 0xA55A0012 178*4882a593SmuzhiyunRTCOR_D: .long 0xA55A001C 179*4882a593SmuzhiyunRTCSR_A: .long SBSC_RTCSR 180*4882a593SmuzhiyunRFCR_A: .long SBSC_RFCR 181*4882a593SmuzhiyunRFCR_D: .long 0xA55A0221 182*4882a593SmuzhiyunRTCSR_D: .long 0xA55A009a 183*4882a593SmuzhiyunSDMR3_A: .long 0xFE581180 184*4882a593SmuzhiyunSDMR3_D: .long 0x0 185*4882a593Smuzhiyun 186*4882a593SmuzhiyunSR_MASK_D: .long 0xEFFFFF0F 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun .align 2 189*4882a593Smuzhiyun 190*4882a593SmuzhiyunSBSCR_D: .word 0x0044 191*4882a593SmuzhiyunPSCR_D: .word 0x0000 192*4882a593SmuzhiyunRWTCSR_D_1: .word 0xA507 193*4882a593SmuzhiyunRWTCSR_D_2: .word 0xA504 194*4882a593SmuzhiyunRWTCNT_D: .word 0x5A00 195