1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2011-2012
3*4882a593Smuzhiyun * Gerald Kerma <dreagle@doukki.net>
4*4882a593Smuzhiyun * Luka Perkov <luka@openwrt.org>
5*4882a593Smuzhiyun * Simon Baatz <gmbnomis@gmail.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <miiphy.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/arch/cpu.h>
14*4882a593Smuzhiyun #include <asm/arch/soc.h>
15*4882a593Smuzhiyun #include <asm/arch/mpp.h>
16*4882a593Smuzhiyun #include "ib62x0.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
19*4882a593Smuzhiyun
board_early_init_f(void)20*4882a593Smuzhiyun int board_early_init_f(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * default gpio configuration
24*4882a593Smuzhiyun * There are maximum 64 gpios controlled through 2 sets of registers
25*4882a593Smuzhiyun * the below configuration configures mainly initial LED status
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun mvebu_config_gpio(IB62x0_OE_VAL_LOW,
28*4882a593Smuzhiyun IB62x0_OE_VAL_HIGH,
29*4882a593Smuzhiyun IB62x0_OE_LOW, IB62x0_OE_HIGH);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Set SATA activity LEDs to default off */
32*4882a593Smuzhiyun writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
33*4882a593Smuzhiyun /* Multi-Purpose Pins Functionality configuration */
34*4882a593Smuzhiyun static const u32 kwmpp_config[] = {
35*4882a593Smuzhiyun MPP0_NF_IO2,
36*4882a593Smuzhiyun MPP1_NF_IO3,
37*4882a593Smuzhiyun MPP2_NF_IO4,
38*4882a593Smuzhiyun MPP3_NF_IO5,
39*4882a593Smuzhiyun MPP4_NF_IO6,
40*4882a593Smuzhiyun MPP5_NF_IO7,
41*4882a593Smuzhiyun MPP6_SYSRST_OUTn,
42*4882a593Smuzhiyun MPP8_TW_SDA,
43*4882a593Smuzhiyun MPP9_TW_SCK,
44*4882a593Smuzhiyun MPP10_UART0_TXD,
45*4882a593Smuzhiyun MPP11_UART0_RXD,
46*4882a593Smuzhiyun MPP18_NF_IO0,
47*4882a593Smuzhiyun MPP19_NF_IO1,
48*4882a593Smuzhiyun MPP20_SATA1_ACTn,
49*4882a593Smuzhiyun MPP21_SATA0_ACTn,
50*4882a593Smuzhiyun MPP22_GPIO, /* Power LED red */
51*4882a593Smuzhiyun MPP24_GPIO, /* Power off device */
52*4882a593Smuzhiyun MPP25_GPIO, /* Power LED green */
53*4882a593Smuzhiyun MPP27_GPIO, /* USB transfer LED */
54*4882a593Smuzhiyun MPP28_GPIO, /* Reset button */
55*4882a593Smuzhiyun MPP29_GPIO, /* USB Copy button */
56*4882a593Smuzhiyun 0
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun kirkwood_mpp_conf(kwmpp_config, NULL);
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
board_init(void)62*4882a593Smuzhiyun int board_init(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun /* adress of boot parameters */
65*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
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