1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2014 DENX
3*4882a593Smuzhiyun * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Derived from code written by Robert Aigner (ra@spiid.net)
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Itself derived from Beagle Board and 3430 SDP code by
8*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com>
9*4882a593Smuzhiyun * Syed Mohammed Khasim <khasim@ti.com>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <dm.h>
15*4882a593Smuzhiyun #include <netdev.h>
16*4882a593Smuzhiyun #include <ns16550.h>
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun #include <asm/arch/mem.h>
19*4882a593Smuzhiyun #include <asm/arch/mux.h>
20*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
21*4882a593Smuzhiyun #include <i2c.h>
22*4882a593Smuzhiyun #include <asm/mach-types.h>
23*4882a593Smuzhiyun #include <asm/omap_mmc.h>
24*4882a593Smuzhiyun #include "cairo.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * Routine: board_init
30*4882a593Smuzhiyun * Description: Early hardware init.
31*4882a593Smuzhiyun */
board_init(void)32*4882a593Smuzhiyun int board_init(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
35*4882a593Smuzhiyun /* board id for Linux */
36*4882a593Smuzhiyun gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
37*4882a593Smuzhiyun /* boot param addr */
38*4882a593Smuzhiyun gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * Routine: set_muxconf_regs
44*4882a593Smuzhiyun * Description: Setting up the configuration Mux registers specific to the
45*4882a593Smuzhiyun * hardware. Many pins need to be moved from protect to primary
46*4882a593Smuzhiyun * mode.
47*4882a593Smuzhiyun */
set_muxconf_regs(void)48*4882a593Smuzhiyun void set_muxconf_regs(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun MUX_CAIRO();
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)54*4882a593Smuzhiyun int board_mmc_init(bd_t *bis)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun return omap_mmc_init(0, 0, 0, -1, -1);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun #endif
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Routine: get_board_mem_timings
63*4882a593Smuzhiyun * Description: If we use SPL then there is no x-loader nor config header
64*4882a593Smuzhiyun * so we have to setup the DDR timings ourself on the first bank. This
65*4882a593Smuzhiyun * provides the timing values back to the function that configures
66*4882a593Smuzhiyun * the memory.
67*4882a593Smuzhiyun *
68*4882a593Smuzhiyun * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
69*4882a593Smuzhiyun */
get_board_mem_timings(struct board_sdrc_timings * timings)70*4882a593Smuzhiyun void get_board_mem_timings(struct board_sdrc_timings *timings)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun timings->sharing = SAMSUNG_SHARING;
73*4882a593Smuzhiyun timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
74*4882a593Smuzhiyun timings->ctrla = SAMSUNG_V_ACTIMA_165;
75*4882a593Smuzhiyun timings->ctrlb = SAMSUNG_V_ACTIMB_165;
76*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
77*4882a593Smuzhiyun timings->mr = SAMSUNG_V_MR_165;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun #endif
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct ns16550_platdata cairo_serial = {
82*4882a593Smuzhiyun .base = OMAP34XX_UART2,
83*4882a593Smuzhiyun .reg_shift = 2,
84*4882a593Smuzhiyun .clock = V_NS16550_CLK,
85*4882a593Smuzhiyun .fcr = UART_FCR_DEFVAL,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun U_BOOT_DEVICE(cairo_uart) = {
89*4882a593Smuzhiyun "ns16550_serial",
90*4882a593Smuzhiyun &cairo_serial
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* force SPL booting into U-Boot, not Linux */
94*4882a593Smuzhiyun #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)95*4882a593Smuzhiyun int spl_start_uboot(void)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun return 1;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun #endif
100