1*4882a593Smuzhiyun/* Memory sub-system initialization code */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include <config.h> 4*4882a593Smuzhiyun#include <asm/regdef.h> 5*4882a593Smuzhiyun#include <asm/mipsregs.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun .text 8*4882a593Smuzhiyun .set noreorder 9*4882a593Smuzhiyun .set mips32 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun .globl lowlevel_init 12*4882a593Smuzhiyunlowlevel_init: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Step 2) Establish Status Register 16*4882a593Smuzhiyun * (set BEV, clear ERL, clear EXL, clear IE) 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun li t1, 0x00400000 19*4882a593Smuzhiyun mtc0 t1, CP0_STATUS 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Step 3) Establish CP0 Config0 23*4882a593Smuzhiyun * (set K0=3) 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun li t1, 0x00000003 26*4882a593Smuzhiyun mtc0 t1, CP0_CONFIG 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * Step 7) Establish Cause 30*4882a593Smuzhiyun * (set IV bit) 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun li t1, 0x00800000 33*4882a593Smuzhiyun mtc0 t1, CP0_CAUSE 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Establish Wired (and Random) */ 36*4882a593Smuzhiyun mtc0 zero, CP0_WIRED 37*4882a593Smuzhiyun nop 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun jr ra 40*4882a593Smuzhiyun nop 41