1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <asm/addrspace.h> 10*4882a593Smuzhiyun #include <asm/types.h> 11*4882a593Smuzhiyun #include <mach/ar71xx_regs.h> 12*4882a593Smuzhiyun #include <mach/ddr.h> 13*4882a593Smuzhiyun #include <mach/ath79.h> 14*4882a593Smuzhiyun #include <debug_uart.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_UART_BOARD_INIT board_debug_uart_init(void)19*4882a593Smuzhiyunvoid board_debug_uart_init(void) 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun void __iomem *regs; 22*4882a593Smuzhiyun u32 val; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, 25*4882a593Smuzhiyun MAP_NOCACHE); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * GPIO9 as input, GPIO10 as output 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun val = readl(regs + AR71XX_GPIO_REG_OE); 31*4882a593Smuzhiyun val |= QCA953X_GPIO(9); 32*4882a593Smuzhiyun val &= ~QCA953X_GPIO(10); 33*4882a593Smuzhiyun writel(val, regs + AR71XX_GPIO_REG_OE); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Enable GPIO10 as UART0_SOUT 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); 39*4882a593Smuzhiyun val &= ~QCA953X_GPIO_MUX_MASK(16); 40*4882a593Smuzhiyun val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; 41*4882a593Smuzhiyun writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * Enable GPIO9 as UART0_SIN 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); 47*4882a593Smuzhiyun val &= ~QCA953X_GPIO_MUX_MASK(8); 48*4882a593Smuzhiyun val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; 49*4882a593Smuzhiyun writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Enable GPIO10 output 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun val = readl(regs + AR71XX_GPIO_REG_OUT); 55*4882a593Smuzhiyun val |= QCA953X_GPIO(10); 56*4882a593Smuzhiyun writel(val, regs + AR71XX_GPIO_REG_OUT); 57*4882a593Smuzhiyun } 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun board_early_init_f(void)60*4882a593Smuzhiyunint board_early_init_f(void) 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun ddr_init(); 63*4882a593Smuzhiyun ath79_eth_reset(); 64*4882a593Smuzhiyun return 0; 65*4882a593Smuzhiyun } 66