1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * PPC-AG BG0900 Boot setup
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <config.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/iomux-mx28.h>
13*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
14*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
17*4882a593Smuzhiyun #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
18*4882a593Smuzhiyun #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
19*4882a593Smuzhiyun #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun const iomux_cfg_t iomux_setup[] = {
22*4882a593Smuzhiyun /* DUART */
23*4882a593Smuzhiyun MX28_PAD_PWM0__DUART_RX,
24*4882a593Smuzhiyun MX28_PAD_PWM1__DUART_TX,
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* GPMI NAND */
27*4882a593Smuzhiyun MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
28*4882a593Smuzhiyun MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
29*4882a593Smuzhiyun MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
30*4882a593Smuzhiyun MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
31*4882a593Smuzhiyun MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
32*4882a593Smuzhiyun MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
33*4882a593Smuzhiyun MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
34*4882a593Smuzhiyun MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
35*4882a593Smuzhiyun MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
36*4882a593Smuzhiyun MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
37*4882a593Smuzhiyun MX28_PAD_GPMI_RDN__GPMI_RDN |
38*4882a593Smuzhiyun (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
39*4882a593Smuzhiyun MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
40*4882a593Smuzhiyun MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
41*4882a593Smuzhiyun MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
42*4882a593Smuzhiyun MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* FEC0 */
45*4882a593Smuzhiyun MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
46*4882a593Smuzhiyun MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
47*4882a593Smuzhiyun MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
48*4882a593Smuzhiyun MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
49*4882a593Smuzhiyun MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
50*4882a593Smuzhiyun MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
51*4882a593Smuzhiyun MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
52*4882a593Smuzhiyun MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
53*4882a593Smuzhiyun MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* FEC0 Reset */
56*4882a593Smuzhiyun MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
57*4882a593Smuzhiyun (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* EMI */
60*4882a593Smuzhiyun MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
61*4882a593Smuzhiyun MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
62*4882a593Smuzhiyun MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
63*4882a593Smuzhiyun MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
64*4882a593Smuzhiyun MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
65*4882a593Smuzhiyun MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
66*4882a593Smuzhiyun MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
67*4882a593Smuzhiyun MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
68*4882a593Smuzhiyun MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
69*4882a593Smuzhiyun MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
70*4882a593Smuzhiyun MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
71*4882a593Smuzhiyun MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
72*4882a593Smuzhiyun MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
73*4882a593Smuzhiyun MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
74*4882a593Smuzhiyun MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
75*4882a593Smuzhiyun MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
76*4882a593Smuzhiyun MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
77*4882a593Smuzhiyun MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
78*4882a593Smuzhiyun MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
79*4882a593Smuzhiyun MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
80*4882a593Smuzhiyun MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
81*4882a593Smuzhiyun MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
82*4882a593Smuzhiyun MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
83*4882a593Smuzhiyun MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
84*4882a593Smuzhiyun MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
87*4882a593Smuzhiyun MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
88*4882a593Smuzhiyun MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
89*4882a593Smuzhiyun MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
90*4882a593Smuzhiyun MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
91*4882a593Smuzhiyun MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
92*4882a593Smuzhiyun MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
93*4882a593Smuzhiyun MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
94*4882a593Smuzhiyun MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
95*4882a593Smuzhiyun MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
96*4882a593Smuzhiyun MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
97*4882a593Smuzhiyun MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
98*4882a593Smuzhiyun MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
99*4882a593Smuzhiyun MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
100*4882a593Smuzhiyun MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
101*4882a593Smuzhiyun MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
102*4882a593Smuzhiyun MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
103*4882a593Smuzhiyun MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
104*4882a593Smuzhiyun MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
105*4882a593Smuzhiyun MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
106*4882a593Smuzhiyun MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
107*4882a593Smuzhiyun MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
108*4882a593Smuzhiyun MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
109*4882a593Smuzhiyun MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* SPI2 (for SPI flash) */
112*4882a593Smuzhiyun MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
113*4882a593Smuzhiyun MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
114*4882a593Smuzhiyun MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
115*4882a593Smuzhiyun MX28_PAD_SSP2_SS0__SSP2_D3 |
116*4882a593Smuzhiyun (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
mxs_adjust_memory_params(uint32_t * dram_vals)119*4882a593Smuzhiyun void mxs_adjust_memory_params(uint32_t *dram_vals)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun /*
122*4882a593Smuzhiyun * DDR Controller Registers
123*4882a593Smuzhiyun * Manufacturer: Winbond
124*4882a593Smuzhiyun * Device Part Number: W972GG6JB-25I
125*4882a593Smuzhiyun * Clock Freq.: 200MHz
126*4882a593Smuzhiyun * Density: 2Gb
127*4882a593Smuzhiyun * Chip Selects: 1
128*4882a593Smuzhiyun * Number of Banks: 8
129*4882a593Smuzhiyun * Row address: 14
130*4882a593Smuzhiyun * Column address: 10
131*4882a593Smuzhiyun */
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun dram_vals[0x74 / 4] = 0x0102010A;
134*4882a593Smuzhiyun dram_vals[0x98 / 4] = 0x04005003;
135*4882a593Smuzhiyun dram_vals[0x9c / 4] = 0x090000c8;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun dram_vals[0xa8 / 4] = 0x0036b009;
138*4882a593Smuzhiyun dram_vals[0xac / 4] = 0x03270612;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun dram_vals[0xb0 / 4] = 0x02020202;
141*4882a593Smuzhiyun dram_vals[0xb4 / 4] = 0x00c80029;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun dram_vals[0xc0 / 4] = 0x00011900;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun dram_vals[0x12c / 4] = 0x07400300;
146*4882a593Smuzhiyun dram_vals[0x130 / 4] = 0x07400300;
147*4882a593Smuzhiyun dram_vals[0x2c4 / 4] = 0x02030303;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
board_init_ll(const uint32_t arg,const uint32_t * resptr)150*4882a593Smuzhiyun void board_init_ll(const uint32_t arg, const uint32_t *resptr)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
153*4882a593Smuzhiyun }
154