1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Maintainer : Steve Sakoman <steve@sakoman.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by 5*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 6*4882a593Smuzhiyun * Syed Mohammed Khasim <khasim@ti.com> 7*4882a593Smuzhiyun * Sunil Kumar <sunilsaini05@gmail.com> 8*4882a593Smuzhiyun * Shashi Ranjan <shashiranjanmca05@gmail.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * (C) Copyright 2004-2008 11*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #include <asm/io.h> 16*4882a593Smuzhiyun #include <asm/arch/mem.h> 17*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 18*4882a593Smuzhiyun #include "overo.h" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Routine: get_board_mem_timings 22*4882a593Smuzhiyun * Description: If we use SPL then there is no x-loader nor config header 23*4882a593Smuzhiyun * so we have to setup the DDR timings ourself on both banks. 24*4882a593Smuzhiyun */ get_board_mem_timings(struct board_sdrc_timings * timings)25*4882a593Smuzhiyunvoid get_board_mem_timings(struct board_sdrc_timings *timings) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun timings->mr = MICRON_V_MR_165; 28*4882a593Smuzhiyun switch (get_board_revision()) { 29*4882a593Smuzhiyun case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ 30*4882a593Smuzhiyun timings->mcfg = MICRON_V_MCFG_165(256 << 20); 31*4882a593Smuzhiyun timings->ctrla = MICRON_V_ACTIMA_165; 32*4882a593Smuzhiyun timings->ctrlb = MICRON_V_ACTIMB_165; 33*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 34*4882a593Smuzhiyun break; 35*4882a593Smuzhiyun case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ 36*4882a593Smuzhiyun case REVISION_4: 37*4882a593Smuzhiyun timings->mcfg = MICRON_V_MCFG_200(256 << 20); 38*4882a593Smuzhiyun timings->ctrla = MICRON_V_ACTIMA_200; 39*4882a593Smuzhiyun timings->ctrlb = MICRON_V_ACTIMB_200; 40*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 41*4882a593Smuzhiyun break; 42*4882a593Smuzhiyun case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ 43*4882a593Smuzhiyun timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 44*4882a593Smuzhiyun timings->ctrla = HYNIX_V_ACTIMA_200; 45*4882a593Smuzhiyun timings->ctrlb = HYNIX_V_ACTIMB_200; 46*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 47*4882a593Smuzhiyun break; 48*4882a593Smuzhiyun case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ 49*4882a593Smuzhiyun timings->mcfg = MCFG(512 << 20, 15); 50*4882a593Smuzhiyun timings->ctrla = MICRON_V_ACTIMA_200; 51*4882a593Smuzhiyun timings->ctrlb = MICRON_V_ACTIMB_200; 52*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 53*4882a593Smuzhiyun break; 54*4882a593Smuzhiyun default: 55*4882a593Smuzhiyun timings->mcfg = MICRON_V_MCFG_165(128 << 20); 56*4882a593Smuzhiyun timings->ctrla = MICRON_V_ACTIMA_165; 57*4882a593Smuzhiyun timings->ctrlb = MICRON_V_ACTIMB_165; 58*4882a593Smuzhiyun timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 59*4882a593Smuzhiyun } 60*4882a593Smuzhiyun } 61