xref: /OK3568_Linux_fs/u-boot/board/nvidia/venice2/venice2.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2013-2014
3*4882a593Smuzhiyun  * NVIDIA Corporation <www.nvidia.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:     GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/arch/gpio.h>
10*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
11*4882a593Smuzhiyun #include "pinmux-config-venice2.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun  * Routine: pinmux_init
15*4882a593Smuzhiyun  * Description: Do individual peripheral pinmux configs
16*4882a593Smuzhiyun  */
pinmux_init(void)17*4882a593Smuzhiyun void pinmux_init(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun 	pinmux_set_tristate_input_clamping();
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun 	gpio_config_table(venice2_gpio_inits,
22*4882a593Smuzhiyun 			  ARRAY_SIZE(venice2_gpio_inits));
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun 	pinmux_config_pingrp_table(venice2_pingrps,
25*4882a593Smuzhiyun 				   ARRAY_SIZE(venice2_pingrps));
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	pinmux_config_drvgrp_table(venice2_drvgrps,
28*4882a593Smuzhiyun 				   ARRAY_SIZE(venice2_drvgrps));
29*4882a593Smuzhiyun }
30