1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010,2011
3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/mach-types.h>
11*4882a593Smuzhiyun #include <asm/arch/tegra.h>
12*4882a593Smuzhiyun #include <asm/arch-tegra/board.h>
13*4882a593Smuzhiyun #include <asm/arch/clock.h>
14*4882a593Smuzhiyun #include <asm/arch/funcmux.h>
15*4882a593Smuzhiyun #include <asm/arch/gpio.h>
16*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
17*4882a593Smuzhiyun #include <asm/gpio.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* TODO: Remove this code when the SPI switch is working */
20*4882a593Smuzhiyun #if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
gpio_early_init_uart(void)21*4882a593Smuzhiyun void gpio_early_init_uart(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
24*4882a593Smuzhiyun gpio_request(TEGRA_GPIO(I, 3), "uart_en");
25*4882a593Smuzhiyun gpio_direction_output(TEGRA_GPIO(I, 3), 0);
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun #endif
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #ifdef CONFIG_MMC_SDHCI_TEGRA
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * Routine: pin_mux_mmc
32*4882a593Smuzhiyun * Description: setup the pin muxes/tristate values for the SDMMC(s)
33*4882a593Smuzhiyun */
pin_mux_mmc(void)34*4882a593Smuzhiyun void pin_mux_mmc(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
37*4882a593Smuzhiyun funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* For power GPIO PI6 */
40*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_ATA);
41*4882a593Smuzhiyun /* For CD GPIO PI5 */
42*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_ATC);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun #endif
45*4882a593Smuzhiyun
pin_mux_usb(void)46*4882a593Smuzhiyun void pin_mux_usb(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun /* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
49*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_SLXK);
50*4882a593Smuzhiyun /* For USB1's ULPI signals */
51*4882a593Smuzhiyun funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
52*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
53*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
54*4882a593Smuzhiyun /* USB1 PHY reset GPIO */
55*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_UAC);
56*4882a593Smuzhiyun }
57