1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013-2015 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _MAX77620_INIT_H_ 9*4882a593Smuzhiyun #define _MAX77620_INIT_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* MAX77620-PMIC-specific early init regs */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MAX77620_I2C_ADDR 0x78 14*4882a593Smuzhiyun #define MAX77620_I2C_ADDR_7BIT 0x3C 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MAX77620_CNFGGLBL1_REG 0x00 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MAX77620_SD0_REG 0x16 19*4882a593Smuzhiyun #define MAX77620_SD1_REG 0x17 20*4882a593Smuzhiyun #define MAX77620_SD2_REG 0x18 21*4882a593Smuzhiyun #define MAX77620_SD3_REG 0x19 22*4882a593Smuzhiyun #define MAX77620_CNFG2SD_REG 0x22 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define MAX77620_CNFG1_L0_REG 0x23 25*4882a593Smuzhiyun #define MAX77620_CNFG2_L0_REG 0x24 26*4882a593Smuzhiyun #define MAX77620_CNFG1_L1_REG 0x25 27*4882a593Smuzhiyun #define MAX77620_CNFG2_L1_REG 0x26 28*4882a593Smuzhiyun #define MAX77620_CNFG1_L2_REG 0x27 29*4882a593Smuzhiyun #define MAX77620_CNFG2_L2_REG 0x28 30*4882a593Smuzhiyun #define MAX77620_CNFG1_L3_REG 0x29 31*4882a593Smuzhiyun #define MAX77620_CNFG2_L3_REG 0x2A 32*4882a593Smuzhiyun #define MAX77620_CNFG1_L4_REG 0x2B 33*4882a593Smuzhiyun #define MAX77620_CNFG2_L4_REG 0x2C 34*4882a593Smuzhiyun #define MAX77620_CNFG1_L5_REG 0x2D 35*4882a593Smuzhiyun #define MAX77620_CNFG2_L5_REG 0x2E 36*4882a593Smuzhiyun #define MAX77620_CNFG1_L6_REG 0x2F 37*4882a593Smuzhiyun #define MAX77620_CNFG2_L6_REG 0x30 38*4882a593Smuzhiyun #define MAX77620_CNFG1_L7_REG 0x31 39*4882a593Smuzhiyun #define MAX77620_CNFG2_L7_REG 0x32 40*4882a593Smuzhiyun #define MAX77620_CNFG1_L8_REG 0x33 41*4882a593Smuzhiyun #define MAX77620_CNFG2_L8_REG 0x34 42*4882a593Smuzhiyun #define MAX77620_CNFG3_LDO_REG 0x35 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MAX77620_GPIO0_REG 0x36 45*4882a593Smuzhiyun #define MAX77620_GPIO1_REG 0x37 46*4882a593Smuzhiyun #define MAX77620_GPIO2_REG 0x38 47*4882a593Smuzhiyun #define MAX77620_GPIO3_REG 0x39 48*4882a593Smuzhiyun #define MAX77620_GPIO4_REG 0x3A 49*4882a593Smuzhiyun #define MAX77620_GPIO5_REG 0x3B 50*4882a593Smuzhiyun #define MAX77620_GPIO6_REG 0x3C 51*4882a593Smuzhiyun #define MAX77620_GPIO7_REG 0x3D 52*4882a593Smuzhiyun #define MAX77620_GPIO_PUE_GPIO 0x3E 53*4882a593Smuzhiyun #define MAX77620_GPIO_PDE_GPIO 0x3F 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define MAX77620_AME_GPIO 0x40 56*4882a593Smuzhiyun #define MAX77620_REG_ONOFF_CFG1 0x41 57*4882a593Smuzhiyun #define MAX77620_REG_ONOFF_CFG2 0x42 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define MAX77620_CID0_REG 0x58 60*4882a593Smuzhiyun #define MAX77620_CID1_REG 0x59 61*4882a593Smuzhiyun #define MAX77620_CID2_REG 0x5A 62*4882a593Smuzhiyun #define MAX77620_CID3_REG 0x5B 63*4882a593Smuzhiyun #define MAX77620_CID4_REG 0x5C 64*4882a593Smuzhiyun #define MAX77620_CID5_REG 0x5D 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define I2C_SEND_2_BYTES 0x0A02 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun void pmic_enable_cpu_vdd(void); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* _MAX77620_INIT_H_ */ 71