1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * To generate this file, use the tegra-pinmux-scripts tool available from 11*4882a593Smuzhiyun * https://github.com/NVIDIA/tegra-pinmux-scripts 12*4882a593Smuzhiyun * Run "board-to-uboot.py p2371-0000". 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _PINMUX_CONFIG_P2371_0000_H_ 16*4882a593Smuzhiyun #define _PINMUX_CONFIG_P2371_0000_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define GPIO_INIT(_port, _gpio, _init) \ 19*4882a593Smuzhiyun { \ 20*4882a593Smuzhiyun .gpio = TEGRA_GPIO(_port, _gpio), \ 21*4882a593Smuzhiyun .init = TEGRA_GPIO_INIT_##_init, \ 22*4882a593Smuzhiyun } 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { 25*4882a593Smuzhiyun /* port, pin, init_val */ 26*4882a593Smuzhiyun GPIO_INIT(A, 5, IN), 27*4882a593Smuzhiyun GPIO_INIT(E, 4, OUT0), 28*4882a593Smuzhiyun GPIO_INIT(E, 6, IN), 29*4882a593Smuzhiyun GPIO_INIT(G, 0, IN), 30*4882a593Smuzhiyun GPIO_INIT(G, 3, OUT0), 31*4882a593Smuzhiyun GPIO_INIT(H, 0, OUT0), 32*4882a593Smuzhiyun GPIO_INIT(H, 2, IN), 33*4882a593Smuzhiyun GPIO_INIT(H, 3, OUT0), 34*4882a593Smuzhiyun GPIO_INIT(H, 4, OUT0), 35*4882a593Smuzhiyun GPIO_INIT(H, 5, IN), 36*4882a593Smuzhiyun GPIO_INIT(H, 6, OUT0), 37*4882a593Smuzhiyun GPIO_INIT(H, 7, OUT0), 38*4882a593Smuzhiyun GPIO_INIT(I, 0, OUT0), 39*4882a593Smuzhiyun GPIO_INIT(I, 1, IN), 40*4882a593Smuzhiyun GPIO_INIT(I, 2, OUT0), 41*4882a593Smuzhiyun GPIO_INIT(I, 3, OUT0), 42*4882a593Smuzhiyun GPIO_INIT(K, 4, IN), 43*4882a593Smuzhiyun GPIO_INIT(K, 5, OUT0), 44*4882a593Smuzhiyun GPIO_INIT(K, 6, IN), 45*4882a593Smuzhiyun GPIO_INIT(K, 7, OUT0), 46*4882a593Smuzhiyun GPIO_INIT(L, 0, OUT0), 47*4882a593Smuzhiyun GPIO_INIT(S, 4, OUT0), 48*4882a593Smuzhiyun GPIO_INIT(S, 5, OUT0), 49*4882a593Smuzhiyun GPIO_INIT(S, 6, OUT0), 50*4882a593Smuzhiyun GPIO_INIT(S, 7, OUT0), 51*4882a593Smuzhiyun GPIO_INIT(T, 0, OUT0), 52*4882a593Smuzhiyun GPIO_INIT(T, 1, OUT0), 53*4882a593Smuzhiyun GPIO_INIT(V, 1, OUT0), 54*4882a593Smuzhiyun GPIO_INIT(V, 2, OUT0), 55*4882a593Smuzhiyun GPIO_INIT(V, 5, OUT0), 56*4882a593Smuzhiyun GPIO_INIT(V, 6, OUT0), 57*4882a593Smuzhiyun GPIO_INIT(V, 7, OUT1), 58*4882a593Smuzhiyun GPIO_INIT(X, 0, IN), 59*4882a593Smuzhiyun GPIO_INIT(X, 1, IN), 60*4882a593Smuzhiyun GPIO_INIT(X, 2, IN), 61*4882a593Smuzhiyun GPIO_INIT(X, 3, IN), 62*4882a593Smuzhiyun GPIO_INIT(X, 4, IN), 63*4882a593Smuzhiyun GPIO_INIT(X, 5, IN), 64*4882a593Smuzhiyun GPIO_INIT(X, 6, IN), 65*4882a593Smuzhiyun GPIO_INIT(X, 7, IN), 66*4882a593Smuzhiyun GPIO_INIT(Y, 1, IN), 67*4882a593Smuzhiyun GPIO_INIT(Z, 0, IN), 68*4882a593Smuzhiyun GPIO_INIT(Z, 4, OUT0), 69*4882a593Smuzhiyun GPIO_INIT(BB, 2, OUT0), 70*4882a593Smuzhiyun GPIO_INIT(BB, 3, OUT0), 71*4882a593Smuzhiyun GPIO_INIT(CC, 1, IN), 72*4882a593Smuzhiyun GPIO_INIT(CC, 6, IN), 73*4882a593Smuzhiyun GPIO_INIT(CC, 7, OUT0), 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ 77*4882a593Smuzhiyun { \ 78*4882a593Smuzhiyun .pingrp = PMUX_PINGRP_##_pingrp, \ 79*4882a593Smuzhiyun .func = PMUX_FUNC_##_mux, \ 80*4882a593Smuzhiyun .pull = PMUX_PULL_##_pull, \ 81*4882a593Smuzhiyun .tristate = PMUX_TRI_##_tri, \ 82*4882a593Smuzhiyun .io = PMUX_PIN_##_io, \ 83*4882a593Smuzhiyun .od = PMUX_PIN_OD_##_od, \ 84*4882a593Smuzhiyun .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ 85*4882a593Smuzhiyun .lock = PMUX_PIN_LOCK_DEFAULT, \ 86*4882a593Smuzhiyun } 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun static const struct pmux_pingrp_config p2371_0000_pingrps[] = { 89*4882a593Smuzhiyun /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ 90*4882a593Smuzhiyun PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), 91*4882a593Smuzhiyun PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), 92*4882a593Smuzhiyun PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), 93*4882a593Smuzhiyun PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), 94*4882a593Smuzhiyun PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), 95*4882a593Smuzhiyun PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 96*4882a593Smuzhiyun PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 97*4882a593Smuzhiyun PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 98*4882a593Smuzhiyun PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 99*4882a593Smuzhiyun PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 100*4882a593Smuzhiyun PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 101*4882a593Smuzhiyun PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 102*4882a593Smuzhiyun PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 103*4882a593Smuzhiyun PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 104*4882a593Smuzhiyun PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 105*4882a593Smuzhiyun PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), 106*4882a593Smuzhiyun PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), 107*4882a593Smuzhiyun PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), 108*4882a593Smuzhiyun PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), 109*4882a593Smuzhiyun PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), 110*4882a593Smuzhiyun PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 111*4882a593Smuzhiyun PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 112*4882a593Smuzhiyun PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 113*4882a593Smuzhiyun PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 114*4882a593Smuzhiyun PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 115*4882a593Smuzhiyun PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), 116*4882a593Smuzhiyun PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 117*4882a593Smuzhiyun PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), 118*4882a593Smuzhiyun PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 119*4882a593Smuzhiyun PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), 120*4882a593Smuzhiyun PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 121*4882a593Smuzhiyun PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), 122*4882a593Smuzhiyun PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 123*4882a593Smuzhiyun PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 124*4882a593Smuzhiyun PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 125*4882a593Smuzhiyun PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 126*4882a593Smuzhiyun PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), 127*4882a593Smuzhiyun PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), 128*4882a593Smuzhiyun PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 129*4882a593Smuzhiyun PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 130*4882a593Smuzhiyun PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 131*4882a593Smuzhiyun PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 132*4882a593Smuzhiyun PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 133*4882a593Smuzhiyun PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 134*4882a593Smuzhiyun PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 135*4882a593Smuzhiyun PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 136*4882a593Smuzhiyun PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 137*4882a593Smuzhiyun PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 138*4882a593Smuzhiyun PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 139*4882a593Smuzhiyun PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 140*4882a593Smuzhiyun PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 141*4882a593Smuzhiyun PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 142*4882a593Smuzhiyun PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 143*4882a593Smuzhiyun PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 144*4882a593Smuzhiyun PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 145*4882a593Smuzhiyun PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 146*4882a593Smuzhiyun PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 147*4882a593Smuzhiyun PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 148*4882a593Smuzhiyun PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), 149*4882a593Smuzhiyun PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), 150*4882a593Smuzhiyun PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), 151*4882a593Smuzhiyun PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), 152*4882a593Smuzhiyun PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 153*4882a593Smuzhiyun PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 154*4882a593Smuzhiyun PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 155*4882a593Smuzhiyun PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 156*4882a593Smuzhiyun PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), 157*4882a593Smuzhiyun PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), 158*4882a593Smuzhiyun PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), 159*4882a593Smuzhiyun PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), 160*4882a593Smuzhiyun PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 161*4882a593Smuzhiyun PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 162*4882a593Smuzhiyun PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 163*4882a593Smuzhiyun PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 164*4882a593Smuzhiyun PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 165*4882a593Smuzhiyun PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), 166*4882a593Smuzhiyun PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 167*4882a593Smuzhiyun PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), 168*4882a593Smuzhiyun PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), 169*4882a593Smuzhiyun PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), 170*4882a593Smuzhiyun PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), 171*4882a593Smuzhiyun PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), 172*4882a593Smuzhiyun PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 173*4882a593Smuzhiyun PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), 174*4882a593Smuzhiyun PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), 175*4882a593Smuzhiyun PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), 176*4882a593Smuzhiyun PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), 177*4882a593Smuzhiyun PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), 178*4882a593Smuzhiyun PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 179*4882a593Smuzhiyun PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 180*4882a593Smuzhiyun PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), 181*4882a593Smuzhiyun PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), 182*4882a593Smuzhiyun PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 183*4882a593Smuzhiyun PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 184*4882a593Smuzhiyun PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 185*4882a593Smuzhiyun PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 186*4882a593Smuzhiyun PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 187*4882a593Smuzhiyun PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 188*4882a593Smuzhiyun PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 189*4882a593Smuzhiyun PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), 190*4882a593Smuzhiyun PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 191*4882a593Smuzhiyun PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), 192*4882a593Smuzhiyun PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 193*4882a593Smuzhiyun PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 194*4882a593Smuzhiyun PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 195*4882a593Smuzhiyun PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 196*4882a593Smuzhiyun PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 197*4882a593Smuzhiyun PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 198*4882a593Smuzhiyun PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 199*4882a593Smuzhiyun PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 200*4882a593Smuzhiyun PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 201*4882a593Smuzhiyun PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 202*4882a593Smuzhiyun PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 203*4882a593Smuzhiyun PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 204*4882a593Smuzhiyun PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 205*4882a593Smuzhiyun PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 206*4882a593Smuzhiyun PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 207*4882a593Smuzhiyun PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 208*4882a593Smuzhiyun PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 209*4882a593Smuzhiyun PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 210*4882a593Smuzhiyun PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), 211*4882a593Smuzhiyun PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), 212*4882a593Smuzhiyun PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), 213*4882a593Smuzhiyun PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), 214*4882a593Smuzhiyun PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), 215*4882a593Smuzhiyun PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), 216*4882a593Smuzhiyun PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 217*4882a593Smuzhiyun PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 218*4882a593Smuzhiyun PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 219*4882a593Smuzhiyun PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), 220*4882a593Smuzhiyun PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 221*4882a593Smuzhiyun PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 222*4882a593Smuzhiyun PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 223*4882a593Smuzhiyun PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 224*4882a593Smuzhiyun PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 225*4882a593Smuzhiyun PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), 226*4882a593Smuzhiyun PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 227*4882a593Smuzhiyun PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 228*4882a593Smuzhiyun PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 229*4882a593Smuzhiyun PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), 230*4882a593Smuzhiyun PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), 231*4882a593Smuzhiyun PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 232*4882a593Smuzhiyun PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 233*4882a593Smuzhiyun PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), 234*4882a593Smuzhiyun PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), 235*4882a593Smuzhiyun PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), 236*4882a593Smuzhiyun PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), 237*4882a593Smuzhiyun PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 238*4882a593Smuzhiyun PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 239*4882a593Smuzhiyun PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 240*4882a593Smuzhiyun PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 241*4882a593Smuzhiyun PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 242*4882a593Smuzhiyun PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 243*4882a593Smuzhiyun PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), 244*4882a593Smuzhiyun PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 245*4882a593Smuzhiyun PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 246*4882a593Smuzhiyun PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), 247*4882a593Smuzhiyun PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), 248*4882a593Smuzhiyun PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 249*4882a593Smuzhiyun PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 250*4882a593Smuzhiyun PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ 254*4882a593Smuzhiyun { \ 255*4882a593Smuzhiyun .drvgrp = PMUX_DRVGRP_##_drvgrp, \ 256*4882a593Smuzhiyun .slwf = _slwf, \ 257*4882a593Smuzhiyun .slwr = _slwr, \ 258*4882a593Smuzhiyun .drvup = _drvup, \ 259*4882a593Smuzhiyun .drvdn = _drvdn, \ 260*4882a593Smuzhiyun .lpmd = PMUX_LPMD_##_lpmd, \ 261*4882a593Smuzhiyun .schmt = PMUX_SCHMT_##_schmt, \ 262*4882a593Smuzhiyun .hsm = PMUX_HSM_##_hsm, \ 263*4882a593Smuzhiyun } 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = { 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #endif /* PINMUX_CONFIG_P2371_0000_H */ 269