1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014
3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <power/as3722.h>
11*4882a593Smuzhiyun #include <power/pmic.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/arch/gpio.h>
14*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "pinmux-config-jetson-tk1.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Routine: pinmux_init
22*4882a593Smuzhiyun * Description: Do individual peripheral pinmux configs
23*4882a593Smuzhiyun */
pinmux_init(void)24*4882a593Smuzhiyun void pinmux_init(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun pinmux_clear_tristate_input_clamping();
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun gpio_config_table(jetson_tk1_gpio_inits,
29*4882a593Smuzhiyun ARRAY_SIZE(jetson_tk1_gpio_inits));
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun pinmux_config_pingrp_table(jetson_tk1_pingrps,
32*4882a593Smuzhiyun ARRAY_SIZE(jetson_tk1_pingrps));
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
35*4882a593Smuzhiyun ARRAY_SIZE(jetson_tk1_drvgrps));
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
38*4882a593Smuzhiyun ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #ifdef CONFIG_PCI_TEGRA
42*4882a593Smuzhiyun /* TODO: Convert to driver model */
as3722_sd_enable(struct udevice * pmic,unsigned int sd)43*4882a593Smuzhiyun static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun int err;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (sd > 6)
48*4882a593Smuzhiyun return -EINVAL;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
51*4882a593Smuzhiyun if (err) {
52*4882a593Smuzhiyun pr_err("failed to update SD control register: %d", err);
53*4882a593Smuzhiyun return err;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
tegra_pcie_board_init(void)59*4882a593Smuzhiyun int tegra_pcie_board_init(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct udevice *dev;
62*4882a593Smuzhiyun int ret;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun ret = uclass_get_device_by_driver(UCLASS_PMIC,
65*4882a593Smuzhiyun DM_GET_DRIVER(pmic_as3722), &dev);
66*4882a593Smuzhiyun if (ret) {
67*4882a593Smuzhiyun debug("%s: Failed to find PMIC\n", __func__);
68*4882a593Smuzhiyun return ret;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun ret = as3722_sd_enable(dev, 4);
72*4882a593Smuzhiyun if (ret < 0) {
73*4882a593Smuzhiyun pr_err("failed to enable SD4: %d\n", ret);
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun ret = as3722_sd_set_voltage(dev, 4, 0x24);
78*4882a593Smuzhiyun if (ret < 0) {
79*4882a593Smuzhiyun pr_err("failed to set SD4 voltage: %d\n", ret);
80*4882a593Smuzhiyun return ret;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun #endif /* PCI */
86