1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010,2011 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <lcd.h> 10*4882a593Smuzhiyun #include <asm/io.h> 11*4882a593Smuzhiyun #include <asm/arch/clock.h> 12*4882a593Smuzhiyun #include <asm/arch/funcmux.h> 13*4882a593Smuzhiyun #include <asm/arch/pinmux.h> 14*4882a593Smuzhiyun #include <asm/arch/tegra.h> 15*4882a593Smuzhiyun #include <asm/gpio.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifdef CONFIG_MMC_SDHCI_TEGRA 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Routine: pin_mux_mmc 20*4882a593Smuzhiyun * Description: setup the pin muxes/tristate values for the SDMMC(s) 21*4882a593Smuzhiyun */ pin_mux_mmc(void)22*4882a593Smuzhiyunvoid pin_mux_mmc(void) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); 25*4882a593Smuzhiyun funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* For power GPIO PI6 */ 28*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_ATA); 29*4882a593Smuzhiyun /* For CD GPIO PH2 */ 30*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_ATD); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* For power GPIO PT3 */ 33*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_DTB); 34*4882a593Smuzhiyun /* For CD GPIO PI5 */ 35*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_ATC); 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun pin_mux_usb(void)39*4882a593Smuzhiyunvoid pin_mux_usb(void) 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); 42*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); 43*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_CDEV2); 44*4882a593Smuzhiyun /* USB2 PHY reset GPIO */ 45*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_UAC); 46*4882a593Smuzhiyun } 47*4882a593Smuzhiyun pin_mux_display(void)48*4882a593Smuzhiyunvoid pin_mux_display(void) 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); 51*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_SDC); 52*4882a593Smuzhiyun } 53