xref: /OK3568_Linux_fs/u-boot/board/nvidia/e2220-1170/e2220-1170.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2013-2015
3*4882a593Smuzhiyun  * NVIDIA Corporation <www.nvidia.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:     GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <asm/arch/gpio.h>
11*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
12*4882a593Smuzhiyun #include "../p2571/max77620_init.h"
13*4882a593Smuzhiyun #include "pinmux-config-e2220-1170.h"
14*4882a593Smuzhiyun 
pin_mux_mmc(void)15*4882a593Smuzhiyun void pin_mux_mmc(void)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun 	struct udevice *dev;
18*4882a593Smuzhiyun 	uchar val;
19*4882a593Smuzhiyun 	int ret;
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun 	/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
22*4882a593Smuzhiyun 	debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
23*4882a593Smuzhiyun 	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
24*4882a593Smuzhiyun 	if (ret) {
25*4882a593Smuzhiyun 		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
26*4882a593Smuzhiyun 		return;
27*4882a593Smuzhiyun 	}
28*4882a593Smuzhiyun 	/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
29*4882a593Smuzhiyun 	val = 0xF2;
30*4882a593Smuzhiyun 	ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
31*4882a593Smuzhiyun 	if (ret)
32*4882a593Smuzhiyun 		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  * Routine: pinmux_init
37*4882a593Smuzhiyun  * Description: Do individual peripheral pinmux configs
38*4882a593Smuzhiyun  */
pinmux_init(void)39*4882a593Smuzhiyun void pinmux_init(void)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	pinmux_clear_tristate_input_clamping();
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	gpio_config_table(e2220_1170_gpio_inits,
44*4882a593Smuzhiyun 			  ARRAY_SIZE(e2220_1170_gpio_inits));
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	pinmux_config_pingrp_table(e2220_1170_pingrps,
47*4882a593Smuzhiyun 				   ARRAY_SIZE(e2220_1170_pingrps));
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	pinmux_config_drvgrp_table(e2220_1170_drvgrps,
50*4882a593Smuzhiyun 				   ARRAY_SIZE(e2220_1170_drvgrps));
51*4882a593Smuzhiyun }
52