xref: /OK3568_Linux_fs/u-boot/board/nvidia/dalmore/pinmux-config-dalmore.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef _PINMUX_CONFIG_DALMORE_H_
8*4882a593Smuzhiyun #define _PINMUX_CONFIG_DALMORE_H_
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io)		\
11*4882a593Smuzhiyun 	{							\
12*4882a593Smuzhiyun 		.pingrp		= PMUX_PINGRP_##_pingrp,	\
13*4882a593Smuzhiyun 		.func		= PMUX_FUNC_##_mux,		\
14*4882a593Smuzhiyun 		.pull		= PMUX_PULL_##_pull,		\
15*4882a593Smuzhiyun 		.tristate	= PMUX_TRI_##_tri,		\
16*4882a593Smuzhiyun 		.io		= PMUX_PIN_##_io,		\
17*4882a593Smuzhiyun 		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
18*4882a593Smuzhiyun 		.od		= PMUX_PIN_OD_DEFAULT,		\
19*4882a593Smuzhiyun 		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
20*4882a593Smuzhiyun 	}
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)	\
23*4882a593Smuzhiyun 	{							\
24*4882a593Smuzhiyun 		.pingrp		= PMUX_PINGRP_##_pingrp,	\
25*4882a593Smuzhiyun 		.func		= PMUX_FUNC_##_mux,		\
26*4882a593Smuzhiyun 		.pull		= PMUX_PULL_##_pull,		\
27*4882a593Smuzhiyun 		.tristate	= PMUX_TRI_##_tri,		\
28*4882a593Smuzhiyun 		.io		= PMUX_PIN_##_io,		\
29*4882a593Smuzhiyun 		.lock		= PMUX_PIN_LOCK_##_lock,	\
30*4882a593Smuzhiyun 		.od		= PMUX_PIN_OD_##_od,		\
31*4882a593Smuzhiyun 		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
32*4882a593Smuzhiyun 	}
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
35*4882a593Smuzhiyun 	{							\
36*4882a593Smuzhiyun 		.pingrp		= PMUX_PINGRP_##_pingrp,	\
37*4882a593Smuzhiyun 		.func		= PMUX_FUNC_##_mux,		\
38*4882a593Smuzhiyun 		.pull		= PMUX_PULL_##_pull,		\
39*4882a593Smuzhiyun 		.tristate	= PMUX_TRI_##_tri,		\
40*4882a593Smuzhiyun 		.io		= PMUX_PIN_##_io,		\
41*4882a593Smuzhiyun 		.lock		= PMUX_PIN_LOCK_##_lock,	\
42*4882a593Smuzhiyun 		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
43*4882a593Smuzhiyun 		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
44*4882a593Smuzhiyun 	}
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
47*4882a593Smuzhiyun 	{							\
48*4882a593Smuzhiyun 		.pingrp		= PMUX_PINGRP_##_pingrp,	\
49*4882a593Smuzhiyun 		.func		= PMUX_FUNC_##_mux,		\
50*4882a593Smuzhiyun 		.pull		= PMUX_PULL_##_pull,		\
51*4882a593Smuzhiyun 		.tristate	= PMUX_TRI_##_tri,		\
52*4882a593Smuzhiyun 		.io		= PMUX_PIN_##_io,		\
53*4882a593Smuzhiyun 		.lock		= PMUX_PIN_LOCK_##_lock,	\
54*4882a593Smuzhiyun 		.od		= PMUX_PIN_OD_DEFAULT,		\
55*4882a593Smuzhiyun 		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
56*4882a593Smuzhiyun 	}
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)		\
59*4882a593Smuzhiyun 	{								\
60*4882a593Smuzhiyun 		.pingrp     = PMUX_PINGRP_##_pingrp,			\
61*4882a593Smuzhiyun 		.func       = PMUX_FUNC_##_mux,				\
62*4882a593Smuzhiyun 		.pull       = PMUX_PULL_##_pull,			\
63*4882a593Smuzhiyun 		.tristate   = PMUX_TRI_##_tri,				\
64*4882a593Smuzhiyun 		.io         = PMUX_PIN_##_io,				\
65*4882a593Smuzhiyun 		.lock       = PMUX_PIN_LOCK_##_lock,			\
66*4882a593Smuzhiyun 		.od         = PMUX_PIN_OD_##_od,			\
67*4882a593Smuzhiyun 		.ioreset    = PMUX_PIN_IO_RESET_DEFAULT,		\
68*4882a593Smuzhiyun 	}
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define USB_PINMUX CEC_PINMUX
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
73*4882a593Smuzhiyun 	{						\
74*4882a593Smuzhiyun 		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
75*4882a593Smuzhiyun 		.slwf   = _slwf,			\
76*4882a593Smuzhiyun 		.slwr   = _slwr,			\
77*4882a593Smuzhiyun 		.drvup  = _drvup,			\
78*4882a593Smuzhiyun 		.drvdn  = _drvdn,			\
79*4882a593Smuzhiyun 		.lpmd   = PMUX_LPMD_##_lpmd,		\
80*4882a593Smuzhiyun 		.schmt  = PMUX_SCHMT_##_schmt,		\
81*4882a593Smuzhiyun 		.hsm    = PMUX_HSM_##_hsm,		\
82*4882a593Smuzhiyun 	}
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun static struct pmux_pingrp_config tegra114_pinmux_common[] = {
85*4882a593Smuzhiyun 	/* EXTPERIPH1 pinmux */
86*4882a593Smuzhiyun 	DEFAULT_PINMUX(CLK1_OUT_PW4,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	/* I2S0 pinmux */
89*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP1_DIN_PN1,      I2S0,        NORMAL,    TRISTATE, INPUT),
90*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP1_DOUT_PN2,     I2S0,        NORMAL,    NORMAL,   INPUT),
91*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP1_FS_PN0,       I2S0,        NORMAL,    NORMAL,   INPUT),
92*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP1_SCLK_PN3,     I2S0,        NORMAL,    NORMAL,   INPUT),
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	/* I2S1 pinmux */
95*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP2_DIN_PA4,      I2S1,        NORMAL,    TRISTATE, INPUT),
96*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP2_DOUT_PA5,     I2S1,        NORMAL,    NORMAL,   INPUT),
97*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP2_FS_PA2,       I2S1,        NORMAL,    NORMAL,   INPUT),
98*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP2_SCLK_PA3,     I2S1,        NORMAL,    NORMAL,   INPUT),
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	/* I2S3 pinmux */
101*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP4_DIN_PP5,      I2S3,        NORMAL,    NORMAL,   INPUT),
102*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP4_DOUT_PP6,     I2S3,        NORMAL,    NORMAL,   INPUT),
103*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP4_FS_PP4,       I2S3,        NORMAL,    NORMAL,   INPUT),
104*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP4_SCLK_PP7,     I2S3,        NORMAL,    NORMAL,   INPUT),
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	/* CLDVFS pinmux */
107*4882a593Smuzhiyun 	DEFAULT_PINMUX(DVFS_PWM_PX0,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
108*4882a593Smuzhiyun 	DEFAULT_PINMUX(DVFS_CLK_PX2,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	/* ULPI pinmux */
111*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_CLK_PY0,      ULPI,        NORMAL,    NORMAL,   INPUT),
112*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DATA0_PO1,    ULPI,        NORMAL,    NORMAL,   INPUT),
113*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DATA1_PO2,    ULPI,        NORMAL,    NORMAL,   INPUT),
114*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DATA2_PO3,    ULPI,        NORMAL,    NORMAL,   INPUT),
115*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DATA3_PO4,    ULPI,        NORMAL,    NORMAL,   INPUT),
116*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DATA4_PO5,    ULPI,        NORMAL,    NORMAL,   INPUT),
117*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DATA5_PO6,    ULPI,        NORMAL,    NORMAL,   INPUT),
118*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DATA6_PO7,    ULPI,        NORMAL,    NORMAL,   INPUT),
119*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DATA7_PO0,    ULPI,        NORMAL,    NORMAL,   INPUT),
120*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_DIR_PY1,      ULPI,        NORMAL,    TRISTATE, INPUT),
121*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_NXT_PY2,      ULPI,        NORMAL,    TRISTATE, INPUT),
122*4882a593Smuzhiyun 	DEFAULT_PINMUX(ULPI_STP_PY3,      ULPI,        NORMAL,    NORMAL,   OUTPUT),
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* I2C3 pinmux */
125*4882a593Smuzhiyun 	I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
126*4882a593Smuzhiyun 	I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/* VI pinmux */
129*4882a593Smuzhiyun 	VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3,  NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	/* VI_ALT1 pinmux */
132*4882a593Smuzhiyun 	VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	/* VGP4 pinmux */
135*4882a593Smuzhiyun 	VI_PINMUX(PBB4, VGP4,    NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	/* I2C2 pinmux */
138*4882a593Smuzhiyun 	I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
139*4882a593Smuzhiyun 	I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* UARTD pinmux */
142*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_A16_PJ7,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
143*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_A17_PB0,       UARTD,       NORMAL,    TRISTATE, INPUT),
144*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_A18_PB1,       UARTD,       NORMAL,    TRISTATE, INPUT),
145*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_A19_PK7,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/* SPI4 pinmux */
148*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD5_PG5,       SPI4,        NORMAL,    NORMAL,   INPUT),
149*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD6_PG6,       SPI4,        UP,        NORMAL,   INPUT),
150*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD7_PG7,       SPI4,        UP,        NORMAL,   INPUT),
151*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD12_PH4,      RSVD1,       NORMAL,    NORMAL,   OUTPUT),
152*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_CS6_N_PI3,     SPI4,        NORMAL,    NORMAL,   INPUT),
153*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_WR_N_PI0,      SPI4,        NORMAL,    NORMAL,   INPUT),
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	/* PWM1 pinmux */
156*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD9_PH1,       PWM1,        NORMAL,    NORMAL,   OUTPUT),
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* SOC pinmux */
159*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_CS1_N_PJ2,     SOC,         NORMAL,    TRISTATE, INPUT),
160*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_OE_N_PI1,      SOC,         NORMAL,    TRISTATE, INPUT),
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	/* EXTPERIPH2 pinmux */
163*4882a593Smuzhiyun 	DEFAULT_PINMUX(CLK2_OUT_PW5,      EXTPERIPH2,  NORMAL,    NORMAL,   OUTPUT),
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	/* SDMMC1 pinmux */
166*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC1_CLK_PZ0,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
167*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC1_CMD_PZ1,    SDMMC1,      UP,        NORMAL,   INPUT),
168*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC1_DAT0_PY7,   SDMMC1,      UP,        NORMAL,   INPUT),
169*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC1_DAT1_PY6,   SDMMC1,      UP,        NORMAL,   INPUT),
170*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC1_DAT2_PY5,   SDMMC1,      UP,        NORMAL,   INPUT),
171*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC1_DAT3_PY4,   SDMMC1,      UP,        NORMAL,   INPUT),
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	/* SDMMC3 pinmux */
174*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_CLK_PA6,    SDMMC3,      NORMAL,    NORMAL,   INPUT),
175*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_CMD_PA7,    SDMMC3,      UP,        NORMAL,   INPUT),
176*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_DAT0_PB7,   SDMMC3,      UP,        NORMAL,   INPUT),
177*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_DAT1_PB6,   SDMMC3,      UP,        NORMAL,   INPUT),
178*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_DAT2_PB5,   SDMMC3,      UP,        NORMAL,   INPUT),
179*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_DAT3_PB4,   SDMMC3,      UP,        NORMAL,   INPUT),
180*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,  UP,        TRISTATE, INPUT),
181*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,  DOWN,      NORMAL,   INPUT),
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	/* SDMMC4 pinmux */
184*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_CLK_PCC4,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
185*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_CMD_PT7,     SDMMC4,      UP,        NORMAL,   INPUT),
186*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_DAT0_PAA0,   SDMMC4,      UP,        NORMAL,   INPUT),
187*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_DAT1_PAA1,   SDMMC4,      UP,        NORMAL,   INPUT),
188*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_DAT2_PAA2,   SDMMC4,      UP,        NORMAL,   INPUT),
189*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_DAT3_PAA3,   SDMMC4,      UP,        NORMAL,   INPUT),
190*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_DAT4_PAA4,   SDMMC4,      UP,        NORMAL,   INPUT),
191*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_DAT5_PAA5,   SDMMC4,      UP,        NORMAL,   INPUT),
192*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_DAT6_PAA6,   SDMMC4,      UP,        NORMAL,   INPUT),
193*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC4_DAT7_PAA7,   SDMMC4,      UP,        NORMAL,   INPUT),
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	/* BLINK pinmux */
196*4882a593Smuzhiyun 	DEFAULT_PINMUX(CLK_32K_OUT_PA0,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	/* KBC pinmux */
199*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_COL0_PQ0,       KBC,         UP,        NORMAL,   INPUT),
200*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_COL1_PQ1,       KBC,         UP,        NORMAL,   INPUT),
201*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_COL2_PQ2,       KBC,         UP,        NORMAL,   INPUT),
202*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW0_PR0,       KBC,         UP,        NORMAL,   INPUT),
203*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW1_PR1,       KBC,         UP,        NORMAL,   INPUT),
204*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW2_PR2,       KBC,         UP,        NORMAL,   INPUT),
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	/*Audio Codec*/
207*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP3_DIN_PP1,      RSVD1,       NORMAL,    TRISTATE, OUTPUT),
208*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP3_SCLK_PP3,     RSVD1,       NORMAL,    TRISTATE, OUTPUT),
209*4882a593Smuzhiyun 	DEFAULT_PINMUX(PV0,               RSVD1,       NORMAL,    TRISTATE, OUTPUT),
210*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW7_PR7,       RSVD1,       UP,        NORMAL,   INPUT),
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* UARTA pinmux */
213*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW10_PS2,      UARTA,       NORMAL,    TRISTATE, INPUT),
214*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW9_PS1,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	/* I2CPWR pinmux (I2C5) */
217*4882a593Smuzhiyun 	I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
218*4882a593Smuzhiyun 	I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	/* SYSCLK pinmux */
221*4882a593Smuzhiyun 	DEFAULT_PINMUX(SYS_CLK_REQ_PZ5,   SYSCLK,      NORMAL,    NORMAL,   OUTPUT),
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	/* RTCK pinmux */
224*4882a593Smuzhiyun 	DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL,   INPUT),
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	/* CLK pinmux */
227*4882a593Smuzhiyun 	DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    TRISTATE, INPUT),
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	/* PWRON pinmux */
230*4882a593Smuzhiyun 	DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	/* CPU pinmux */
233*4882a593Smuzhiyun 	DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	/* PMI pinmux */
236*4882a593Smuzhiyun 	DEFAULT_PINMUX(PWR_INT_N,     PMI,         NORMAL,    TRISTATE, INPUT),
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	/* RESET_OUT_N pinmux */
239*4882a593Smuzhiyun 	DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	/* EXTPERIPH3 pinmux */
242*4882a593Smuzhiyun 	DEFAULT_PINMUX(CLK3_OUT_PEE0,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	/* I2C1 pinmux */
245*4882a593Smuzhiyun 	I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
246*4882a593Smuzhiyun 	I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	/* UARTB pinmux */
249*4882a593Smuzhiyun 	DEFAULT_PINMUX(UART2_CTS_N_PJ5,   UARTB,       NORMAL,    TRISTATE, INPUT),
250*4882a593Smuzhiyun 	DEFAULT_PINMUX(UART2_RTS_N_PJ6,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	/* IRDA pinmux */
253*4882a593Smuzhiyun 	DEFAULT_PINMUX(UART2_RXD_PC3,     IRDA,        NORMAL,    TRISTATE, INPUT),
254*4882a593Smuzhiyun 	DEFAULT_PINMUX(UART2_TXD_PC2,     IRDA,        NORMAL,    NORMAL,   OUTPUT),
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	/* UARTC pinmux */
257*4882a593Smuzhiyun 	DEFAULT_PINMUX(UART3_CTS_N_PA1,   UARTC,       NORMAL,    TRISTATE, INPUT),
258*4882a593Smuzhiyun 	DEFAULT_PINMUX(UART3_RTS_N_PC0,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
259*4882a593Smuzhiyun 	DEFAULT_PINMUX(UART3_RXD_PW7,     UARTC,       NORMAL,    TRISTATE, INPUT),
260*4882a593Smuzhiyun 	DEFAULT_PINMUX(UART3_TXD_PW6,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	/* OWR pinmux */
263*4882a593Smuzhiyun 	DEFAULT_PINMUX(OWR,               OWR,         NORMAL,    NORMAL,   INPUT),
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	/* CEC pinmux */
266*4882a593Smuzhiyun 	CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	/* I2C4 pinmux */
269*4882a593Smuzhiyun 	DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
270*4882a593Smuzhiyun 	DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	/* USB pinmux */
273*4882a593Smuzhiyun 	USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	/* nct */
276*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_X6_AUD_PX6,   SPI6,        UP,        TRISTATE, INPUT),
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun static struct pmux_pingrp_config unused_pins_lowpower[] = {
280*4882a593Smuzhiyun 	DEFAULT_PINMUX(CLK1_REQ_PEE2,     RSVD3,       DOWN, TRISTATE, OUTPUT),
281*4882a593Smuzhiyun 	DEFAULT_PINMUX(USB_VBUS_EN1_PN5,  RSVD3,       DOWN, TRISTATE, OUTPUT),
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun /* Initially setting all used GPIO's to non-TRISTATE */
285*4882a593Smuzhiyun static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
286*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_X4_AUD_PX4,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
287*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_X5_AUD_PX5,     RSVD1,  UP,      NORMAL,    INPUT),
288*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_X6_AUD_PX6,     RSVD3,  UP,      NORMAL,    INPUT),
289*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_X7_AUD_PX7,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
290*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_W2_AUD_PW2,     RSVD1,  UP,      NORMAL,    INPUT),
291*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_W3_AUD_PW3,     SPI6,   UP,      NORMAL,    INPUT),
292*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_X1_AUD_PX1,     RSVD3,  DOWN,    NORMAL,    INPUT),
293*4882a593Smuzhiyun 	DEFAULT_PINMUX(GPIO_X3_AUD_PX3,     RSVD3,  UP,      NORMAL,    INPUT),
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP3_FS_PP0,         I2S2,   DOWN,    NORMAL,    OUTPUT),
296*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP3_DIN_PP1,        I2S2,   DOWN,    NORMAL,    OUTPUT),
297*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP3_DOUT_PP2,       I2S2,   DOWN,    NORMAL,    OUTPUT),
298*4882a593Smuzhiyun 	DEFAULT_PINMUX(DAP3_SCLK_PP3,       I2S2,   DOWN,    NORMAL,    OUTPUT),
299*4882a593Smuzhiyun 	DEFAULT_PINMUX(PV0,                 RSVD3,  NORMAL,  NORMAL,    INPUT),
300*4882a593Smuzhiyun 	DEFAULT_PINMUX(PV1,                 RSVD1,  NORMAL,  NORMAL,    INPUT),
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	DEFAULT_PINMUX(PBB3,                RSVD3,  DOWN,    NORMAL,    OUTPUT),
303*4882a593Smuzhiyun 	DEFAULT_PINMUX(PBB5,                RSVD3,  DOWN,    NORMAL,    OUTPUT),
304*4882a593Smuzhiyun 	DEFAULT_PINMUX(PBB6,                RSVD3,  DOWN,    NORMAL,    OUTPUT),
305*4882a593Smuzhiyun 	DEFAULT_PINMUX(PBB7,                RSVD3,  DOWN,    NORMAL,    OUTPUT),
306*4882a593Smuzhiyun 	DEFAULT_PINMUX(PCC1,                RSVD3,  DOWN,    NORMAL,    INPUT),
307*4882a593Smuzhiyun 	DEFAULT_PINMUX(PCC2,                RSVD3,  DOWN,    NORMAL,    INPUT),
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD0_PG0,         GMI,    NORMAL,  NORMAL,    OUTPUT),
310*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD1_PG1,         GMI,    NORMAL,  NORMAL,    OUTPUT),
311*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD10_PH2,        GMI,    DOWN,    NORMAL,    OUTPUT),
312*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD11_PH3,        GMI,    DOWN,    NORMAL,    OUTPUT),
313*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD12_PH4,        GMI,    UP,      NORMAL,    INPUT),
314*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD13_PH5,        GMI,    DOWN,    NORMAL,    OUTPUT),
315*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD2_PG2,         GMI,    NORMAL,  NORMAL,    INPUT),
316*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD3_PG3,         GMI,    NORMAL,  NORMAL,    INPUT),
317*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD8_PH0,         GMI,    DOWN,    NORMAL,    OUTPUT),
318*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_ADV_N_PK0,       GMI,    UP,      NORMAL,    INPUT),
319*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_CLK_PK1,         GMI,    DOWN,    NORMAL,    OUTPUT),
320*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_CS0_N_PJ0,       GMI,    UP,      NORMAL,    INPUT),
321*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_CS2_N_PK3,       GMI,    UP,      NORMAL,    INPUT),
322*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_CS3_N_PK4,       GMI,    UP,      NORMAL,    OUTPUT),
323*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_CS4_N_PK2,       GMI,    UP,      NORMAL,    INPUT),
324*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_CS7_N_PI6,       GMI,    UP,      NORMAL,    INPUT),
325*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_DQS_P_PJ3,       GMI,    UP,      NORMAL,    INPUT),
326*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_IORDY_PI5,       GMI,    UP,      NORMAL,    INPUT),
327*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_WP_N_PC7,        GMI,    UP,      NORMAL,    INPUT),
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC1_WP_N_PV3,     SPI4,   UP,      NORMAL,    OUTPUT),
330*4882a593Smuzhiyun 	DEFAULT_PINMUX(CLK2_REQ_PCC5,       RSVD3,  NORMAL,  NORMAL,    OUTPUT),
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_COL3_PQ3,         KBC,    UP,      NORMAL,    OUTPUT),
333*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_COL4_PQ4,         SDMMC3, UP,      NORMAL,    INPUT),
334*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_COL5_PQ5,         KBC,    UP,      NORMAL,    INPUT),
335*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_COL6_PQ6,         KBC,    UP,      NORMAL,    OUTPUT),
336*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_COL7_PQ7,         KBC,    UP,      NORMAL,    OUTPUT),
337*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW3_PR3,         KBC,    DOWN,    NORMAL,    INPUT),
338*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW4_PR4,         KBC,    DOWN,    NORMAL,    INPUT),
339*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW6_PR6,         KBC,    DOWN,    NORMAL,    INPUT),
340*4882a593Smuzhiyun 	DEFAULT_PINMUX(KB_ROW8_PS0,         KBC,    UP,      NORMAL,    INPUT),
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	DEFAULT_PINMUX(CLK3_REQ_PEE1,       RSVD3,  NORMAL,  NORMAL,    OUTPUT),
343*4882a593Smuzhiyun 	DEFAULT_PINMUX(PU4,                 RSVD3,  NORMAL,  NORMAL,    OUTPUT),
344*4882a593Smuzhiyun 	DEFAULT_PINMUX(PU5,                 RSVD3,  NORMAL,  NORMAL,    INPUT),
345*4882a593Smuzhiyun 	DEFAULT_PINMUX(PU6,                 RSVD3,  NORMAL,  NORMAL,    INPUT),
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	DEFAULT_PINMUX(HDMI_INT_PN7,        RSVD1,   DOWN,    NORMAL,   INPUT),
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	DEFAULT_PINMUX(GMI_AD9_PH1,         PWM1,   NORMAL,   NORMAL,   OUTPUT),
350*4882a593Smuzhiyun 	DEFAULT_PINMUX(SPDIF_IN_PK6,        USB,    NORMAL,   NORMAL,   INPUT),
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	DEFAULT_PINMUX(SDMMC3_CD_N_PV2,     SDMMC3, UP,       NORMAL,   INPUT),
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static struct pmux_drvgrp_config dalmore_padctrl[] = {
356*4882a593Smuzhiyun 	/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
357*4882a593Smuzhiyun 	DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
358*4882a593Smuzhiyun 		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
359*4882a593Smuzhiyun };
360*4882a593Smuzhiyun #endif /* PINMUX_CONFIG_COMMON_H */
361