1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010-2013
3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
11*4882a593Smuzhiyun #include <asm/arch/gp_padctrl.h>
12*4882a593Smuzhiyun #include <asm/arch/gpio.h>
13*4882a593Smuzhiyun #include <asm/gpio.h>
14*4882a593Smuzhiyun #include "pinmux-config-cardhu.h"
15*4882a593Smuzhiyun #include <i2c.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define PMU_I2C_ADDRESS 0x2D
18*4882a593Smuzhiyun #define MAX_I2C_RETRY 3
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Routine: pinmux_init
22*4882a593Smuzhiyun * Description: Do individual peripheral pinmux configs
23*4882a593Smuzhiyun */
pinmux_init(void)24*4882a593Smuzhiyun void pinmux_init(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun pinmux_config_pingrp_table(tegra3_pinmux_common,
27*4882a593Smuzhiyun ARRAY_SIZE(tegra3_pinmux_common));
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun pinmux_config_pingrp_table(unused_pins_lowpower,
30*4882a593Smuzhiyun ARRAY_SIZE(unused_pins_lowpower));
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Initialize any non-default pad configs (APB_MISC_GP regs) */
33*4882a593Smuzhiyun pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #if defined(CONFIG_MMC_SDHCI_TEGRA)
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * Do I2C/PMU writes to bring up SD card bus power
39*4882a593Smuzhiyun *
40*4882a593Smuzhiyun */
board_sdmmc_voltage_init(void)41*4882a593Smuzhiyun void board_sdmmc_voltage_init(void)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct udevice *dev;
44*4882a593Smuzhiyun uchar reg, data_buffer[1];
45*4882a593Smuzhiyun int ret;
46*4882a593Smuzhiyun int i;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
49*4882a593Smuzhiyun if (ret) {
50*4882a593Smuzhiyun debug("%s: Cannot find PMIC I2C chip\n", __func__);
51*4882a593Smuzhiyun return;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
55*4882a593Smuzhiyun data_buffer[0] = 0x65;
56*4882a593Smuzhiyun reg = 0x32;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun for (i = 0; i < MAX_I2C_RETRY; ++i) {
59*4882a593Smuzhiyun if (dm_i2c_write(dev, reg, data_buffer, 1))
60*4882a593Smuzhiyun udelay(100);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */
64*4882a593Smuzhiyun data_buffer[0] = 0x09;
65*4882a593Smuzhiyun reg = 0x67;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun for (i = 0; i < MAX_I2C_RETRY; ++i) {
68*4882a593Smuzhiyun if (dm_i2c_write(dev, reg, data_buffer, 1))
69*4882a593Smuzhiyun udelay(100);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * Routine: pin_mux_mmc
75*4882a593Smuzhiyun * Description: setup the MMC muxes, power rails, etc.
76*4882a593Smuzhiyun */
pin_mux_mmc(void)77*4882a593Smuzhiyun void pin_mux_mmc(void)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun * NOTE: We don't do mmc-specific pin muxes here.
81*4882a593Smuzhiyun * They were done globally in pinmux_init().
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Bring up the SDIO1 power rail */
85*4882a593Smuzhiyun board_sdmmc_voltage_init();
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun #endif /* MMC */
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #ifdef CONFIG_PCI_TEGRA
tegra_pcie_board_init(void)90*4882a593Smuzhiyun int tegra_pcie_board_init(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct udevice *dev;
93*4882a593Smuzhiyun u8 addr, data[1];
94*4882a593Smuzhiyun int err;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
97*4882a593Smuzhiyun if (err) {
98*4882a593Smuzhiyun debug("failed to find PMU bus\n");
99*4882a593Smuzhiyun return err;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* TPS659110: LDO1_REG = 1.05V, ACTIVE */
103*4882a593Smuzhiyun data[0] = 0x15;
104*4882a593Smuzhiyun addr = 0x30;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun err = dm_i2c_write(dev, addr, data, 1);
107*4882a593Smuzhiyun if (err) {
108*4882a593Smuzhiyun debug("failed to set VDD supply\n");
109*4882a593Smuzhiyun return err;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* GPIO: PEX = 3.3V */
113*4882a593Smuzhiyun err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
114*4882a593Smuzhiyun if (err < 0)
115*4882a593Smuzhiyun return err;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun gpio_direction_output(TEGRA_GPIO(L, 7), 1);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* TPS659110: LDO2_REG = 1.05V, ACTIVE */
120*4882a593Smuzhiyun data[0] = 0x15;
121*4882a593Smuzhiyun addr = 0x31;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun err = dm_i2c_write(dev, addr, data, 1);
124*4882a593Smuzhiyun if (err) {
125*4882a593Smuzhiyun debug("failed to set AVDD supply\n");
126*4882a593Smuzhiyun return err;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return 0;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun #endif /* PCI */
132