1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2007 3*4882a593Smuzhiyun * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 6*4882a593Smuzhiyun * Kenati Technologies, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * board/ms7722se/lowlevel_init.S 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <config.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun#include <asm/processor.h> 16*4882a593Smuzhiyun#include <asm/macro.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/* 19*4882a593Smuzhiyun * Board specific low level init code, called _very_ early in the 20*4882a593Smuzhiyun * startup sequence. Relocation to SDRAM has not happened yet, no 21*4882a593Smuzhiyun * stack is available, bss section has not been initialised, etc. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * (Note: As no stack is available, no subroutines can be called...). 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun .global lowlevel_init 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun .text 29*4882a593Smuzhiyun .align 2 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunlowlevel_init: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Cache Control Register 35*4882a593Smuzhiyun * Instruction Cache Invalidate 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun write32 CCR_A, CCR_D 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * Address of MMU Control Register 41*4882a593Smuzhiyun * TI == TLB Invalidate bit 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun write32 MMUCR_A, MMUCR_D 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Address of Power Control Register 0 */ 46*4882a593Smuzhiyun write32 MSTPCR0_A, MSTPCR0_D 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Address of Power Control Register 2 */ 49*4882a593Smuzhiyun write32 MSTPCR2_A, MSTPCR2_D 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun write16 SBSCR_A, SBSCR_D 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun write16 PSCR_A, PSCR_D 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 0xA4520004 (Watchdog Control / Status Register) */ 56*4882a593Smuzhiyun! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 0xA4520000 (Watchdog Count Register) */ 59*4882a593Smuzhiyun write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 0xA4520004 (Watchdog Control / Status Register) */ 62*4882a593Smuzhiyun write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 0xA4150000 Frequency control register */ 65*4882a593Smuzhiyun write32 FRQCR_A, FRQCR_D 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun write32 CCR_A, CCR_D_2 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunbsc_init: 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun write16 PSELA_A, PSELA_D 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun write16 DRVCR_A, DRVCR_D 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun write16 PCCR_A, PCCR_D 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun write16 PECR_A, PECR_D 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun write16 PJCR_A, PJCR_D 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun write16 PXCR_A, PXCR_D 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun write32 CMNCR_A, CMNCR_D 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun write32 CS0BCR_A, CS0BCR_D 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun write32 CS2BCR_A, CS2BCR_D 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun write32 CS4BCR_A, CS4BCR_D 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun write32 CS5ABCR_A, CS5ABCR_D 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun write32 CS5BBCR_A, CS5BBCR_D 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun write32 CS6ABCR_A, CS6ABCR_D 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun write32 CS0WCR_A, CS0WCR_D 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun write32 CS2WCR_A, CS2WCR_D 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun write32 CS4WCR_A, CS4WCR_D 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun write32 CS5AWCR_A, CS5AWCR_D 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun write32 CS5BWCR_A, CS5BWCR_D 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun write32 CS6AWCR_A, CS6AWCR_D 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun ! SDRAM initialization 110*4882a593Smuzhiyun write32 SDCR_A, SDCR_D 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun write32 SDWCR_A, SDWCR_D 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun write32 SDPCR_A, SDPCR_D 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun write32 RTCOR_A, RTCOR_D 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun write32 RTCSR_A, RTCSR_D 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun write8 SDMR3_A, SDMR3_D 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun ! BL bit off (init = ON) (?!?) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun stc sr, r0 ! BL bit off(init=ON) 125*4882a593Smuzhiyun mov.l SR_MASK_D, r1 126*4882a593Smuzhiyun and r1, r0 127*4882a593Smuzhiyun ldc r0, sr 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun rts 130*4882a593Smuzhiyun mov #0, r0 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun .align 2 133*4882a593Smuzhiyun 134*4882a593SmuzhiyunCCR_A: .long CCR 135*4882a593SmuzhiyunMMUCR_A: .long MMUCR 136*4882a593SmuzhiyunMSTPCR0_A: .long MSTPCR0 137*4882a593SmuzhiyunMSTPCR2_A: .long MSTPCR2 138*4882a593SmuzhiyunSBSCR_A: .long SBSCR 139*4882a593SmuzhiyunPSCR_A: .long PSCR 140*4882a593SmuzhiyunRWTCSR_A: .long RWTCSR 141*4882a593SmuzhiyunRWTCNT_A: .long RWTCNT 142*4882a593SmuzhiyunFRQCR_A: .long FRQCR 143*4882a593Smuzhiyun 144*4882a593SmuzhiyunCCR_D: .long 0x00000800 145*4882a593SmuzhiyunCCR_D_2: .long 0x00000103 146*4882a593SmuzhiyunMMUCR_D: .long 0x00000004 147*4882a593SmuzhiyunMSTPCR0_D: .long 0x00001001 148*4882a593SmuzhiyunMSTPCR2_D: .long 0xffffffff 149*4882a593SmuzhiyunFRQCR_D: .long 0x07022538 150*4882a593Smuzhiyun 151*4882a593SmuzhiyunPSELA_A: .long 0xa405014E 152*4882a593SmuzhiyunPSELA_D: .word 0x0A10 153*4882a593Smuzhiyun .align 2 154*4882a593Smuzhiyun 155*4882a593SmuzhiyunDRVCR_A: .long 0xa405018A 156*4882a593SmuzhiyunDRVCR_D: .word 0x0554 157*4882a593Smuzhiyun .align 2 158*4882a593Smuzhiyun 159*4882a593SmuzhiyunPCCR_A: .long 0xa4050104 160*4882a593SmuzhiyunPCCR_D: .word 0x8800 161*4882a593Smuzhiyun .align 2 162*4882a593Smuzhiyun 163*4882a593SmuzhiyunPECR_A: .long 0xa4050108 164*4882a593SmuzhiyunPECR_D: .word 0x0000 165*4882a593Smuzhiyun .align 2 166*4882a593Smuzhiyun 167*4882a593SmuzhiyunPJCR_A: .long 0xa4050110 168*4882a593SmuzhiyunPJCR_D: .word 0x1000 169*4882a593Smuzhiyun .align 2 170*4882a593Smuzhiyun 171*4882a593SmuzhiyunPXCR_A: .long 0xa4050148 172*4882a593SmuzhiyunPXCR_D: .word 0x0AAA 173*4882a593Smuzhiyun .align 2 174*4882a593Smuzhiyun 175*4882a593SmuzhiyunCMNCR_A: .long CMNCR 176*4882a593SmuzhiyunCMNCR_D: .long 0x00000013 177*4882a593SmuzhiyunCS0BCR_A: .long CS0BCR ! Flash bank 1 178*4882a593SmuzhiyunCS0BCR_D: .long 0x24920400 179*4882a593SmuzhiyunCS2BCR_A: .long CS2BCR ! SRAM 180*4882a593SmuzhiyunCS2BCR_D: .long 0x24920400 181*4882a593SmuzhiyunCS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot 182*4882a593SmuzhiyunCS4BCR_D: .long 0x24920400 183*4882a593SmuzhiyunCS5ABCR_A: .long CS5ABCR ! Ext slot 184*4882a593SmuzhiyunCS5ABCR_D: .long 0x24920400 185*4882a593SmuzhiyunCS5BBCR_A: .long CS5BBCR ! USB controller 186*4882a593SmuzhiyunCS5BBCR_D: .long 0x24920400 187*4882a593SmuzhiyunCS6ABCR_A: .long CS6ABCR ! Ethernet 188*4882a593SmuzhiyunCS6ABCR_D: .long 0x24920400 189*4882a593Smuzhiyun 190*4882a593SmuzhiyunCS0WCR_A: .long CS0WCR 191*4882a593SmuzhiyunCS0WCR_D: .long 0x00000300 192*4882a593SmuzhiyunCS2WCR_A: .long CS2WCR 193*4882a593SmuzhiyunCS2WCR_D: .long 0x00000300 194*4882a593SmuzhiyunCS4WCR_A: .long CS4WCR 195*4882a593SmuzhiyunCS4WCR_D: .long 0x00000300 196*4882a593SmuzhiyunCS5AWCR_A: .long CS5AWCR 197*4882a593SmuzhiyunCS5AWCR_D: .long 0x00000300 198*4882a593SmuzhiyunCS5BWCR_A: .long CS5BWCR 199*4882a593SmuzhiyunCS5BWCR_D: .long 0x00000300 200*4882a593SmuzhiyunCS6AWCR_A: .long CS6AWCR 201*4882a593SmuzhiyunCS6AWCR_D: .long 0x00000300 202*4882a593Smuzhiyun 203*4882a593SmuzhiyunSDCR_A: .long SBSC_SDCR 204*4882a593SmuzhiyunSDCR_D: .long 0x00020809 205*4882a593SmuzhiyunSDWCR_A: .long SBSC_SDWCR 206*4882a593SmuzhiyunSDWCR_D: .long 0x00164d0d 207*4882a593SmuzhiyunSDPCR_A: .long SBSC_SDPCR 208*4882a593SmuzhiyunSDPCR_D: .long 0x00000087 209*4882a593SmuzhiyunRTCOR_A: .long SBSC_RTCOR 210*4882a593SmuzhiyunRTCOR_D: .long 0xA55A0034 211*4882a593SmuzhiyunRTCSR_A: .long SBSC_RTCSR 212*4882a593SmuzhiyunRTCSR_D: .long 0xA55A0010 213*4882a593SmuzhiyunSDMR3_A: .long 0xFE500180 214*4882a593SmuzhiyunSDMR3_D: .long 0x0 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun .align 1 217*4882a593Smuzhiyun 218*4882a593SmuzhiyunSBSCR_D: .word 0x0040 219*4882a593SmuzhiyunPSCR_D: .word 0x0000 220*4882a593SmuzhiyunRWTCSR_D_1: .word 0xA507 221*4882a593SmuzhiyunRWTCSR_D_2: .word 0xA507 222*4882a593SmuzhiyunRWTCNT_D: .word 0x5A00 223*4882a593Smuzhiyun .align 2 224*4882a593Smuzhiyun 225*4882a593SmuzhiyunSR_MASK_D: .long 0xEFFFFF0F 226